Lines Matching refs:SI_CC_IDX
233 cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
548 origidx = SI_CC_IDX;
585 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 100);
656 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
684 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol),
1407 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), ~0, 0x2);
1431 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, pmuwatchdog), ~0, ticks);
1439 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
2520 si_corereg(&sii->pub, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol), ~0, w);
2725 return (si_setcoreidx(sih, SI_CC_IDX));
2747 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
2769 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
2791 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
2871 return (si_corereg(sih, SI_CC_IDX, regoff, 0, 0));
2892 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
2913 return (si_corereg(sih, SI_CC_IDX, regoff, mask, val));
2927 return (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
2941 return (si_corereg(sih, SI_CC_IDX,
2956 return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
2978 return (si_corereg(sih, SI_CC_IDX, offs, mask, val));
3075 return (si_corereg(sih, SI_CC_IDX, offs, CI_GPIO, (enable ? CI_GPIO : 0)));
3423 si_corereg(sih, SI_CC_IDX, (sih->ccrev < 35 ?
3444 si_corereg(sih, SI_CC_IDX, offset, mask, val);
3448 si_corereg(sih, SI_CC_IDX,
3473 si_corereg(sih, SI_CC_IDX, offset, CLKCTL_STS_SECI_CLK_REQ, val);
3602 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0xFF); /* 4MBaud */
3608 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x44);
3612 si_corereg(sih, SI_CC_IDX, offset, 0xFF, 0x22);
3617 si_corereg(sih, SI_CC_IDX, offset, 0xFF,
3620 si_corereg(sih, SI_CC_IDX, offset,
3625 si_corereg(sih, SI_CC_IDX, offset, 0xFFFFFFFF, ECI_MACCTRLLO_BITS);
3627 si_corereg(sih, SI_CC_IDX, offset, 0xFFFF, ECI_MACCTRLHI_BITS);
3898 cc = si_setcoreidx(sih, SI_CC_IDX);