Lines Matching defs:sii
48 static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh, void *regs,
50 static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid, void *sdh);
51 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
53 static void si_nvram_process(si_info_t *sii, char *pvars);
60 static bool _si_clkctl_cc(si_info_t *sii, uint mode);
61 static bool si_ispcie(si_info_t *sii);
62 static uint BCMINITFN(socram_banksize)(si_info_t *sii, sbsocramregs_t *r, uint8 idx, uint8 mtype);
83 si_info_t *sii;
86 if ((sii = MALLOC(osh, sizeof (si_info_t))) == NULL) {
91 if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
92 MFREE(osh, sii, sizeof(si_info_t));
95 sii->vars = vars ? *vars : NULL;
96 sii->varsz = varsz ? *varsz : 0;
98 return (si_t *)sii;
155 si_info_t *sii = SI_INFO(sih);
158 void *regs = sii->curmap;
161 rev_id = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_REV, sizeof(uint32));
174 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
175 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32), SI_ENUM_BASE);
182 W_REG(sii->osh, &cc->regcontrol_addr, 0);
183 /* AND_REG(sii->osh, &cc->regcontrol_data, ~0x80); */
184 W_REG(sii->osh, &cc->regcontrol_data, 0x3001);
189 W_REG(sii->osh, &cc->min_res_mask, 0x0d);
191 SPINWAIT(((ccst = OSL_PCI_READ_CONFIG(sii->osh, PCI_CLK_CTL_ST, 4)) & CCS_ALPAVAIL)
200 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32), w);
206 BCMATTACHFN(si_buscore_prep)(si_info_t *sii, uint bustype, uint devid, void *sdh)
210 sii->memseg = TRUE;
213 if (!si_ldo_war((si_t *)sii, devid))
218 if (BUSTYPE(bustype) == PCI_BUS && !si_ispcie(sii))
219 si_clkctl_xtal(&sii->pub, XTAL|PLL, ON);
226 BCMATTACHFN(si_buscore_setup)(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
233 cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
237 sii->pub.ccrev = (int)si_corerev(&sii->pub);
240 if (sii->pub.ccrev >= 11)
241 sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);
244 sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities);
247 if (sii->pub.ccrev >= 35)
248 sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext);
251 if (sii->pub.cccaps & CC_CAP_PMU) {
252 sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities);
253 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
257 sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,
258 sii->pub.pmucaps));
261 sii->pub.buscoretype = NODEV_CORE_ID;
262 sii->pub.buscorerev = NOREV;
263 sii->pub.buscoreidx = BADIDX;
269 for (i = 0; i < sii->numcores; i++) {
272 si_setcoreidx(&sii->pub, i);
273 cid = si_coreid(&sii->pub);
274 crev = si_corerev(&sii->pub);
278 i, cid, crev, sii->coresba[i], sii->regs[i]));
292 sii->pub.buscorerev = crev;
293 sii->pub.buscoretype = cid;
294 sii->pub.buscoreidx = i;
298 if ((savewin && (savewin == sii->coresba[i])) ||
299 (regs == sii->regs[i]))
304 if (si_ispcie(sii))
310 sii->pub.buscoretype = PCI_CORE_ID;
311 sii->pub.buscorerev = pcirev;
312 sii->pub.buscoreidx = pciidx;
314 sii->pub.buscoretype = PCIE_CORE_ID;
315 sii->pub.buscorerev = pcierev;
316 sii->pub.buscoreidx = pcieidx;
319 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx, sii->pub.buscoretype,
320 sii->pub.buscorerev));
322 if (BUSTYPE(sii->pub.bustype) == SI_BUS && (CHIPID(sii->pub.chip) == BCM4712_CHIP_ID) &&
323 (sii->pub.chippkg != BCM4712LARGE_PKG_ID) && (CHIPREV(sii->pub.chiprev) <= 3))
324 OR_REG(sii->osh, &cc->slow_clk_ctl, SCC_SS_XTAL);
327 if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
328 if (SI_FAST(sii)) {
329 if (!sii->pch &&
330 ((sii->pch = (void *)(uintptr)pcicore_init(&sii->pub, sii->osh,
331 (void *)PCIEREGS(sii))) == NULL))
334 if (si_pci_fixcfg(&sii->pub)) {
342 si_setcoreidx(&sii->pub, *origidx);
348 BCMATTACHFN(si_nvram_process)(si_info_t *sii, char *pvars)
351 if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) {
353 sii->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
357 switch (BUSTYPE(sii->pub.bustype)) {
360 sii->pub.boardvendor = VENDOR_BROADCOM;
361 sii->pub.boardtype = getintvar(pvars, "boardtype");
364 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32));
366 if ((sii->pub.boardvendor = (uint16)si_getdevpathintvar(&sii->pub, "boardvendor"))
368 sii->pub.boardvendor = w & 0xffff;
371 sii->pub.boardvendor, w & 0xffff));
372 if ((sii->pub.boardtype = (uint16)si_getdevpathintvar(&sii->pub, "boardtype"))
374 sii->pub.boardtype = (w >> 16) & 0xffff;
377 sii->pub.boardtype, (w >> 16) & 0xffff));
382 sii->pub.boardvendor = getintvar(pvars, "manfid");
383 sii->pub.boardtype = getintvar(pvars, "prodid");
389 sii->pub.boardvendor = VENDOR_BROADCOM;
390 if (pvars == NULL || ((sii->pub.boardtype = getintvar(pvars, "prodid")) == 0))
391 if ((sii->pub.boardtype = getintvar(NULL, "boardtype")) == 0)
392 sii->pub.boardtype = 0xffff;
394 if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) {
396 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(uint32));
397 sii->pub.boardvendor = w & 0xffff;
398 sii->pub.boardtype = (w >> 16) & 0xffff;
403 if (sii->pub.boardtype == 0) {
405 ASSERT(sii->pub.boardtype);
408 sii->pub.boardrev = getintvar(pvars, "boardrev");
409 sii->pub.boardflags = getintvar(pvars, "boardflags");
451 BCMATTACHFN(si_doattach)(si_info_t *sii, uint devid, osl_t *osh, void *regs,
454 struct si_pub *sih = &sii->pub;
462 bzero((uchar*)sii, sizeof(si_info_t));
468 sii->curmap = regs;
469 sii->sdh = sdh;
470 sii->osh = osh;
478 (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff)) {
486 savewin = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
489 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE);
503 if (!si_buscore_prep(sii, bustype, devid, sdh)) {
527 if (CHIPTYPE(sii->pub.socitype) == SOCI_SB) {
529 sb_scan(&sii->pub, regs, devid);
530 } else if (CHIPTYPE(sii->pub.socitype) == SOCI_AI) {
533 ai_scan(&sii->pub, (void *)(uintptr)cc, devid);
534 } else if (CHIPTYPE(sii->pub.socitype) == SOCI_UBUS) {
537 ub_scan(&sii->pub, (void *)(uintptr)cc, devid);
543 if (sii->numcores == 0) {
549 if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
563 if ((sii->pub.ccrev == 0x25) && ((CHIPID(sih->chip) == BCM43236_CHIP_ID ||
567 (CHIPREV(sii->pub.chiprev) <= 2))) {
596 nvram_init((void *)&(sii->pub));
599 if (srom_var_init(&sii->pub, BUSTYPE(bustype), regs, sii->osh, vars, varsz)) {
604 si_nvram_process(sii, pvars);
631 if (sii->pub.ccrev >= 20) {
641 si_pmu_init(sih, sii->osh);
642 si_pmu_chip_init(sih, sii->osh);
646 xtalfreq = si_pmu_measure_alpclk(sih, sii->osh);
647 si_pmu_pll_init(sih, sii->osh, xtalfreq);
648 si_pmu_res_init(sih, sii->osh);
649 si_pmu_swreg_init(sih, sii->osh);
653 if (sii->pub.ccrev >= 16) {
659 if (PCI_FORCEHT(sii)) {
663 _si_clkctl_cc(sii, CLK_FAST);
667 if (PCIE(sii)) {
668 ASSERT(sii->pch != NULL);
670 pcicore_attach(sii->pch, pvars, SI_DOATTACH);
704 return (sii);
708 if (sii->pch)
709 pcicore_deinit(sii->pch);
710 sii->pch = NULL;
720 si_info_t *sii;
728 sii = SI_INFO(sih);
730 if (sii == NULL)
735 if (sii->regs[idx]) {
736 REG_UNMAP(sii->regs[idx]);
737 sii->regs[idx] = NULL;
745 if (sii->pch)
746 pcicore_deinit(sii->pch);
747 sii->pch = NULL;
751 if (sii != &ksii)
753 MFREE(sii->osh, sii, sizeof(si_info_t));
759 si_info_t *sii;
761 sii = SI_INFO(sih);
762 return sii->osh;
768 si_info_t *sii;
770 sii = SI_INFO(sih);
771 if (sii->osh != NULL) {
773 ASSERT(!sii->osh);
775 sii->osh = osh;
783 si_info_t *sii;
785 sii = SI_INFO(sih);
786 sii->intr_arg = intr_arg;
787 sii->intrsoff_fn = (si_intrsoff_t)intrsoff_fn;
788 sii->intrsrestore_fn = (si_intrsrestore_t)intrsrestore_fn;
789 sii->intrsenabled_fn = (si_intrsenabled_t)intrsenabled_fn;
793 sii->dev_coreid = sii->coreid[sii->curidx];
799 si_info_t *sii;
801 sii = SI_INFO(sih);
802 sii->intrsoff_fn = NULL;
808 si_info_t *sii = SI_INFO(sih);
813 return R_REG(sii->osh, ((uint32 *)(uintptr)
814 (sii->oob_router + OOB_STATUSA)));
852 si_info_t *sii;
854 sii = SI_INFO(sih);
855 return sii->coreid[sii->curidx];
861 si_info_t *sii;
863 sii = SI_INFO(sih);
864 return sii->curidx;
871 si_info_t *sii;
877 sii = SI_INFO(sih);
880 idx = sii->curidx;
882 ASSERT(GOODREGS(sii->curmap));
887 if (sii->coreid[i] == coreid)
933 si_info_t *sii;
937 sii = SI_INFO(sih);
941 for (i = 0; i < sii->numcores; i++)
942 if (sii->coreid[i] == coreid) {
955 si_info_t *sii;
957 sii = SI_INFO(sih);
959 bcopy((uchar*)sii->coreid, (uchar*)coreid, (sii->numcores * sizeof(uint)));
960 return (sii->numcores);
967 si_info_t *sii;
969 sii = SI_INFO(sih);
970 ASSERT(GOODREGS(sii->curmap));
972 return (sii->curmap);
1021 si_info_t *sii;
1023 sii = SI_INFO(sih);
1025 if (SI_FAST(sii)) {
1032 return (void *)CCREGS_FAST(sii);
1034 return (void *)PCIEREGS(sii);
1036 INTR_OFF(sii, *intr_val);
1037 *origidx = sii->curidx;
1048 si_info_t *sii;
1050 sii = SI_INFO(sih);
1051 if (SI_FAST(sii) && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
1055 INTR_RESTORE(sii, intr_val);
1337 si_info_t *sii;
1344 sii = SI_INFO(sih);
1345 INTR_OFF(sii, intr_val);
1347 rate = si_pmu_si_clock(sih, sii->osh);
1351 idx = sii->curidx;
1355 n = R_REG(sii->osh, &cc->clockcontrol_n);
1358 m = R_REG(sii->osh, &cc->clockcontrol_m3);
1360 m = R_REG(sii->osh, &cc->clockcontrol_m2);
1362 m = R_REG(sii->osh, &cc->clockcontrol_sb);
1373 INTR_RESTORE(sii, intr_val);
1470 si_info_t *sii = SI_INFO(sih);
1482 else if ((device = (uint16)getintvar(sii->vars, "devid")) != 0)
1485 else if ((device = (uint16)getintvar(sii->vars, "wl0id")) != 0)
1650 si_info_t *sii;
1653 sii = SI_INFO(sih);
1654 origidx = sii->curidx;
1656 INTR_OFF(sii, intr_val);
1667 INTR_RESTORE(sii, intr_val);
1674 si_slowclk_src(si_info_t *sii)
1678 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
1680 if (sii->pub.ccrev < 6) {
1681 if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) &&
1682 (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)) &
1687 } else if (sii->pub.ccrev < 10) {
1688 cc = (chipcregs_t *)si_setcoreidx(&sii->pub, sii->curidx);
1689 return (R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
1696 si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
1701 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
1704 ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL);
1706 slowclk = si_slowclk_src(sii);
1707 if (sii->pub.ccrev < 6) {
1712 } else if (sii->pub.ccrev < 10) {
1714 (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
1725 div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
1733 BCMINITFN(si_clkctl_setdelay)(si_info_t *sii, void *chipcregs)
1745 slowclk = si_slowclk_src(sii);
1750 slowmaxfreq = si_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? FALSE : TRUE, cc);
1755 W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay);
1756 W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay);
1763 si_info_t *sii;
1771 sii = SI_INFO(sih);
1772 fast = SI_FAST(sii);
1774 origidx = sii->curidx;
1777 } else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)
1783 SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
1786 si_clkctl_setdelay(sii, (void *)(uintptr)cc);
1796 si_info_t *sii;
1804 sii = SI_INFO(sih);
1806 INTR_OFF(sii, intr_val);
1807 fpdelay = si_pmu_fast_pwrup_delay(sih, sii->osh);
1808 INTR_RESTORE(sii, intr_val);
1815 fast = SI_FAST(sii);
1818 origidx = sii->curidx;
1819 INTR_OFF(sii, intr_val);
1823 else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)
1827 slowminfreq = si_slowclk_freq(sii, FALSE, cc);
1828 fpdelay = (((R_REG(sii->osh, &cc->pll_on_delay) + 2) * 1000000) +
1834 INTR_RESTORE(sii, intr_val);
1843 si_info_t *sii;
1846 sii = SI_INFO(sih);
1857 if (PCIE(sii))
1860 in = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_IN, sizeof(uint32));
1861 out = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32));
1862 outen = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN, sizeof(uint32));
1883 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
1885 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN,
1893 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
1902 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32), out);
1903 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN, sizeof(uint32),
1923 si_info_t *sii;
1925 sii = SI_INFO(sih);
1931 if (PCI_FORCEHT(sii))
1934 return _si_clkctl_cc(sii, mode);
1939 _si_clkctl_cc(si_info_t *sii, uint mode)
1945 bool fast = SI_FAST(sii);
1948 if (sii->pub.ccrev < 6)
1952 ASSERT(sii->pub.ccrev != 10);
1955 INTR_OFF(sii, intr_val);
1956 origidx = sii->curidx;
1958 if ((BUSTYPE(sii->pub.bustype) == SI_BUS) &&
1959 si_setcore(&sii->pub, MIPS33_CORE_ID, 0) &&
1960 (si_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10))
1963 cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0);
1964 } else if ((cc = (chipcregs_t *) CCREGS_FAST(sii)) == NULL)
1968 if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20))
1973 if (sii->pub.ccrev < 10) {
1975 si_clkctl_xtal(&sii->pub, XTAL, ON);
1976 SET_REG(sii->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
1977 } else if (sii->pub.ccrev < 20) {
1978 OR_REG(sii->osh, &cc->system_clk_ctl, SYCC_HR);
1980 OR_REG(sii->osh, &cc->clk_ctl_st, CCS_FORCEHT);
1984 if (PMUCTL_ENAB(&sii->pub)) {
1986 if (CHIPID(sii->pub.chip) == BCM4328_CHIP_ID)
1988 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail) == 0),
1990 ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail);
1997 if (sii->pub.ccrev < 10) {
1998 scc = R_REG(sii->osh, &cc->slow_clk_ctl);
2002 W_REG(sii->osh, &cc->slow_clk_ctl, scc);
2006 si_clkctl_xtal(&sii->pub, XTAL, OFF);
2007 } else if (sii->pub.ccrev < 20) {
2009 AND_REG(sii->osh, &cc->system_clk_ctl, ~SYCC_HR);
2011 AND_REG(sii->osh, &cc->clk_ctl_st, ~CCS_FORCEHT);
2021 si_setcoreidx(&sii->pub, origidx);
2022 INTR_RESTORE(sii, intr_val);
2176 si_info_t *sii;
2178 sii = SI_INFO(sih);
2180 if (!PCIE(sii)) {
2185 return pcicore_pciereg(sii->pch, offset, mask, val, type);
2191 si_info_t *sii;
2193 sii = SI_INFO(sih);
2195 if (!PCIE(sii)) {
2200 return pcicore_pcieserdesreg(sii->pch, mdioslave, offset, mask, val);
2206 si_ispcie(si_info_t *sii)
2210 if (BUSTYPE(sii->pub.bustype) != PCI_BUS)
2213 cap_ptr = pcicore_find_pci_capability(sii->osh, PCI_CAP_PCIECAP_ID, NULL, NULL);
2225 si_info_t *sii;
2227 sii = SI_INFO(sih);
2229 pcicore_pmeen(sii->pch);
2236 si_info_t *sii;
2238 sii = SI_INFO(sih);
2240 return pcicore_pmestat(sii->pch);
2247 si_info_t *sii;
2249 sii = SI_INFO(sih);
2251 pcicore_pmeclr(sii->pch);
2258 si_info_t *sii;
2261 sii = SI_INFO(sih);
2264 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
2266 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
2274 si_info_t *sii;
2276 sii = SI_INFO(sih);
2278 return (PCI(sii) && (sih->buscorerev <= 10));
2289 si_info_t *sii;
2291 sii = SI_INFO(sih);
2293 if (!PCIE(sii))
2296 pcie_war_ovr_aspm_update(sii->pch, aspm);
2302 si_info_t *sii;
2304 sii = SI_INFO(sih);
2306 if (!PCIE(sii))
2309 pcie_power_save_enable(sii->pch, enable);
2315 si_info_t *sii;
2317 sii = SI_INFO(sih);
2319 if (!PCIE(sii))
2322 pcie_set_request_size(sii->pch, size);
2328 si_info_t *sii;
2330 sii = SI_INFO(sih);
2332 if (!PCIE(sii))
2335 return pcie_get_request_size(sii->pch);
2342 si_info_t *sii;
2344 sii = SI_INFO(sih);
2346 sii->pub.chippkg = val;
2352 si_info_t *sii;
2354 sii = SI_INFO(sih);
2360 if (PCI_FORCEHT(sii))
2361 _si_clkctl_cc(sii, CLK_FAST);
2363 if (PCIE(sii)) {
2364 pcicore_up(sii->pch, SI_PCIUP);
2367 sb_set_initiator_to((void *)sii, 0x3,
2368 si_findcoreidx((void *)sii, D11_CORE_ID, 0));
2376 si_info_t *sii;
2378 sii = SI_INFO(sih);
2380 pcicore_sleep(sii->pch);
2387 si_info_t *sii;
2389 sii = SI_INFO(sih);
2396 if (PCI_FORCEHT(sii))
2397 _si_clkctl_cc(sii, CLK_DYNAMIC);
2399 pcicore_down(sii->pch, SI_PCIDOWN);
2409 si_info_t *sii;
2414 sii = SI_INFO(sih);
2416 if (BUSTYPE(sii->pub.bustype) != PCI_BUS)
2419 ASSERT(PCI(sii) || PCIE(sii));
2420 ASSERT(sii->pub.buscoreidx != BADIDX);
2422 if (PCI(sii)) {
2424 idx = sii->curidx;
2430 pciregs = (sbpciregs_t *)si_setcoreidx(sih, sii->pub.buscoreidx);
2437 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {
2439 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32));
2445 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_MASK, sizeof(uint32), w);
2451 if (PCI(sii)) {
2452 OR_REG(sii->osh, &pciregs->sbtopci2, (SBTOPCI_PREF | SBTOPCI_BURST));
2453 if (sii->pub.buscorerev >= 11) {
2454 OR_REG(sii->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
2455 w = R_REG(sii->osh, &pciregs->clkrun);
2456 W_REG(sii->osh, &pciregs->clkrun, (w | PCI_CLKRUN_DSBL));
2457 w = R_REG(sii->osh, &pciregs->clkrun);
2468 si_info_t *sii;
2470 sii = SI_INFO(sih);
2472 if (!(PCIE(sii)))
2474 return pcie_clkreq(sii->pch, mask, val);
2480 si_info_t *sii;
2482 sii = SI_INFO(sih);
2484 if (!PCIE(sii))
2487 return pcie_lcreg(sii->pch, mask, val);
2513 si_info_t *sii = SI_INFO(sih);
2515 ASSERT(BUSTYPE(sii->pub.bustype) == PCI_BUS);
2517 if ((CHIPID(sii->pub.chip) == BCM4321_CHIP_ID) && (CHIPREV(sii->pub.chiprev) < 2)) {
2518 w = (CHIPREV(sii->pub.chiprev) == 0) ?
2520 si_corereg(&sii->pub, SI_CC_IDX, OFFSETOF(chipcregs_t, chipcontrol), ~0, w);
2525 origidx = si_coreidx(&sii->pub);
2528 if (sii->pub.buscoretype == PCIE_CORE_ID) {
2529 pcieregs = (sbpcieregs_t *)si_setcore(&sii->pub, PCIE_CORE_ID, 0);
2533 } else if (sii->pub.buscoretype == PCI_CORE_ID) {
2534 pciregs = (sbpciregs_t *)si_setcore(&sii->pub, PCI_CORE_ID, 0);
2539 pciidx = si_coreidx(&sii->pub);
2540 val16 = R_REG(sii->osh, reg16);
2543 W_REG(sii->osh, reg16, val16);
2547 si_setcoreidx(&sii->pub, origidx);
2549 pcicore_hwup(sii->pch);
2558 si_info_t *sii;
2561 sii = SI_INFO(sih);
2564 sii, sih->chip, sih->chiprev, sih->boardtype, sih->boardvendor, sih->bustype);
2566 sii->osh, sii->curmap);
2570 sih->ccrev, sih->buscoretype, sih->buscorerev, sii->curidx);
2574 for (i = 0; i < sii->numcores; i++)
2575 bcm_bprintf(b, "0x%x ", sii->coreid[i]);
2582 si_info_t *sii;
2587 sii = SI_INFO(sih);
2588 origidx = sii->curidx;
2594 INTR_OFF(sii, intr_val);
2622 INTR_RESTORE(sii, intr_val);
2629 si_info_t *sii;
2637 sii = SI_INFO(sih);
2638 INTR_OFF(sii, intr_val);
2639 origidx = sii->curidx;
2654 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(uint32)),
2655 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN, sizeof(uint32)));
2664 INTR_RESTORE(sii, intr_val);
2670 si_info_t *sii;
2672 sii = SI_INFO(sih);
2674 if (!PCIE(sii))
2677 return pcicore_dump_pcieregs(sii->pch, b);
2683 si_info_t *sii;
2688 sii = SI_INFO(sih);
2690 INTR_OFF(sii, intr_val);
2699 bcm_bprintf(b, "gpioin 0x%x ", R_REG(sii->osh, &cc->gpioin));
2700 bcm_bprintf(b, "gpioout 0x%x ", R_REG(sii->osh, &cc->gpioout));
2701 bcm_bprintf(b, "gpioouten 0x%x ", R_REG(sii->osh, &cc->gpioouten));
2702 bcm_bprintf(b, "gpiocontrol 0x%x ", R_REG(sii->osh, &cc->gpiocontrol));
2703 bcm_bprintf(b, "gpiointpolarity 0x%x ", R_REG(sii->osh, &cc->gpiointpolarity));
2704 bcm_bprintf(b, "gpiointmask 0x%x ", R_REG(sii->osh, &cc->gpiointmask));
2706 if (sii->pub.ccrev >= 16) {
2707 bcm_bprintf(b, "gpiotimerval 0x%x ", R_REG(sii->osh, &cc->gpiotimerval));
2708 bcm_bprintf(b, "gpiotimeroutmask 0x%x", R_REG(sii->osh, &cc->gpiotimeroutmask));
2715 INTR_RESTORE(sii, intr_val);
2798 si_info_t *sii;
2800 sii = SI_INFO(sih);
2833 si_info_t *sii;
2835 sii = SI_INFO(sih);
2864 si_info_t *sii;
2867 sii = SI_INFO(sih);
2878 si_info_t *sii;
2881 sii = SI_INFO(sih);
2899 si_info_t *sii;
2902 sii = SI_INFO(sih);
2920 si_info_t *sii;
2922 sii = SI_INFO(sih);
2934 si_info_t *sii;
2936 sii = SI_INFO(sih);
2948 si_info_t *sii;
2951 sii = SI_INFO(sih);
2962 si_info_t *sii;
2965 sii = SI_INFO(sih);
2985 si_info_t *sii;
2991 sii = SI_INFO(sih);
2995 if ((gi = MALLOC(sii->osh, sizeof(gpioh_item_t))) == NULL)
3004 gi->next = sii->gpioh_head;
3005 sii->gpioh_head = gi;
3013 si_info_t *sii;
3016 sii = SI_INFO(sih);
3020 ASSERT(sii->gpioh_head != NULL);
3021 if ((void*)sii->gpioh_head == gpioh) {
3022 sii->gpioh_head = sii->gpioh_head->next;
3023 MFREE(sii->osh, gpioh, sizeof(gpioh_item_t));
3026 p = sii->gpioh_head;
3031 MFREE(sii->osh, gpioh, sizeof(gpioh_item_t));
3045 si_info_t *sii;
3051 sii = SI_INFO(sih);
3052 for (h = sii->gpioh_head; h != NULL; h = h->next) {
3067 si_info_t *sii;
3070 sii = SI_INFO(sih);
3081 socram_banksize(si_info_t *sii, sbsocramregs_t *regs, uint8 index, uint8 mem_type)
3088 W_REG(sii->osh, ®s->bankidx, bankidx);
3089 bankinfo = R_REG(sii->osh, ®s->bankinfo);
3097 si_info_t *sii;
3104 sii = SI_INFO(sih);
3107 INTR_OFF(sii, intr_val);
3128 extcinfo = R_REG(sii->osh, ®s->extracoreinfo);
3132 W_REG(sii->osh, ®s->bankidx, bankidx);
3133 bankinfo = R_REG(sii->osh, ®s->bankinfo);
3142 W_REG(sii->osh, ®s->bankinfo, bankinfo);
3160 INTR_RESTORE(sii, intr_val);
3175 si_info_t *sii;
3183 sii = SI_INFO(sih);
3186 INTR_OFF(sii, intr_val);
3203 extcinfo = R_REG(sii->osh, ®s->extracoreinfo);
3206 memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_DEVRAM);
3215 INTR_RESTORE(sii, intr_val);
3224 si_info_t *sii;
3234 sii = SI_INFO(sih);
3237 INTR_OFF(sii, intr_val);
3248 coreinfo = R_REG(sii->osh, ®s->coreinfo);
3269 memsize += socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);
3278 INTR_RESTORE(sii, intr_val);
3343 si_info_t *sii;
3352 sii = SI_INFO(sih);
3353 fast = SI_FAST(sii);
3355 origidx = sii->curidx;
3358 } else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)
3364 W_REG(sii->osh, &cc->eci.lt35.eci_intmaskhi, 0x0);
3365 W_REG(sii->osh, &cc->eci.lt35.eci_intmaskmi, 0x0);
3366 W_REG(sii->osh, &cc->eci.lt35.eci_intmasklo, 0x0);
3369 W_REG(sii->osh, &cc->eci.ge35.eci_intmaskhi, 0x0);
3370 W_REG(sii->osh, &cc->eci.ge35.eci_intmasklo, 0x0);
3375 W_REG(sii->osh, &cc->eci.lt35.eci_control, ECI_MACCTRL_BITS);
3378 W_REG(sii->osh, &cc->eci.ge35.eci_controllo, ECI_MACCTRLLO_BITS);
3379 W_REG(sii->osh, &cc->eci.ge35.eci_controlhi, ECI_MACCTRLHI_BITS);
3386 W_REG(sii->osh, &cc->eci.lt35.eci_eventmaskhi, 0x0);
3387 W_REG(sii->osh, &cc->eci.lt35.eci_eventmaskmi, 0x0);
3388 W_REG(sii->osh, &cc->eci.lt35.eci_eventmasklo, 0x0);
3391 W_REG(sii->osh, &cc->eci.ge35.eci_eventmaskhi, 0x0);
3392 W_REG(sii->osh, &cc->eci.ge35.eci_eventmasklo, 0x0);
3493 si_info_t *sii;
3501 sii = SI_INFO(sih);
3502 fast = SI_FAST(sii);
3505 origidx = sii->curidx;
3508 } else if ((cc = (chipcregs_t *)CCREGS_FAST(sii)) == NULL)
3513 seci_conf = R_REG(sii->osh, &cc->SECI_config);
3515 W_REG(sii->osh, &cc->SECI_config, seci_conf);
3517 W_REG(sii->osh, &cc->SECI_config, seci_conf);
3533 si_info_t *sii;
3549 sii = SI_INFO(sih);
3550 fast = SI_FAST(sii);
3552 origidx = sii->curidx;
3555 } else if ((ptr = CCREGS_FAST(sii)) == NULL)
3564 regval = R_REG(sii->osh, &cc->chipcontrol);
3566 W_REG(sii->osh, &cc->chipcontrol, regval);
3568 regval = R_REG(sii->osh, &cc->jtagctrl);
3570 W_REG(sii->osh, &cc->jtagctrl, regval);
3577 seci_conf = R_REG(sii->osh, &cc->SECI_config);
3579 W_REG(sii->osh, &cc->SECI_config, seci_conf);
3581 W_REG(sii->osh, &cc->SECI_config, seci_conf);
3590 W_REG(sii->osh, &cc->SECI_config, seci_conf);
3593 seci_conf = R_REG(sii->osh, &cc->SECI_config);
3595 W_REG(sii->osh, &cc->SECI_config, seci_conf);
3631 seci_conf = R_REG(sii->osh, &cc->SECI_config);
3634 W_REG(sii->osh, &cc->SECI_config, seci_conf);
3637 seci_conf = R_REG(sii->osh, &cc->SECI_config);
3639 W_REG(sii->osh, &cc->SECI_config, seci_conf);
3652 si_info_t *sii;
3657 sii = SI_INFO(sih);
3666 INTR_OFF(sii, intr_val);
3673 W_REG(sii->osh, &cc->uart0mcr, R_REG(sii->osh, &cc->uart0mcr) | 0x04);
3678 INTR_RESTORE(sii, intr_val);
3685 si_info_t *sii;
3689 sii = SI_INFO(sih);
3692 W_REG(sii->osh, &cc->chipcontrol, val);
3699 si_info_t *sii;
3704 sii = SI_INFO(sih);
3707 val = R_REG(sii->osh, &cc->chipcontrol);
3715 si_info_t *sii;
3720 sii = SI_INFO(sih);
3725 val = R_REG(sii->osh, &cc->chipcontrol);
3731 W_REG(sii->osh, &cc->chipcontrol, val);
3735 W_REG(sii->osh, &cc->chipcontrol, val |
3738 W_REG(sii->osh, &cc->chipcontrol, val | (CCTRL4331_EXTPA_EN));
3743 W_REG(sii->osh, &cc->chipcontrol, val);
3752 si_info_t *sii;
3765 sii = SI_INFO(sih);
3770 val = R_REG(sii->osh, &cc->chipcontrol);
3774 W_REG(sii->osh, &cc->chipcontrol, val);
3777 W_REG(sii->osh, &cc->chipcontrol, val);
3789 si_info_t *sii;
3790 sii = SI_INFO(sih);
3791 INTR_OFF(sii, intr_val);
3792 err = si_pll_minresmask_reset(sih, sii->osh);
3793 INTR_RESTORE(sii, intr_val);
3801 si_info_t *sii;
3805 sii = SI_INFO(sih);
3811 W_REG(sii->osh, &cc->gpiocontrol,
3812 R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
3820 si_info_t *sii;
3821 sii = SI_INFO(sih);
3823 si_pmu_minresmask_htavail_set(sih, sii->osh, set_clear);
3830 si_info_t *sii;
3834 sii = SI_INFO(sih);
3838 W_REG(sii->osh, &cc->gpiocontrol,
3839 R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_5_6_EN_MASK);
3841 W_REG(sii->osh, &cc->gpioouten,
3842 R_REG(sii->osh, &cc->gpioouten) | GPIO_CTRL_5_6_EN_MASK);
3849 si_info_t *sii;
3853 sii = SI_INFO(sih);
3859 W_REG(sii->osh, &cc->chipcontrol,
3860 R_REG(sii->osh, &cc->chipcontrol) | CC_BTCOEX_EN_MASK);
3869 si_info_t *sii;
3871 sii = SI_INFO(sih);
3875 ASSERT(sii->osh != NULL);
3876 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_VID, sizeof(uint32));
3888 si_info_t *sii;
3896 sii = SI_INFO(sih);
3897 origidx = sii->curidx;
3899 sromctrl = R_REG(sii->osh, &cc->sromcontrol);