Lines Matching defs:sii
38 static uint _sb_coreidx(si_info_t *sii, uint32 sba);
39 static uint _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba,
41 static uint32 _sb_coresba(si_info_t *sii);
42 static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
44 #define SET_SBREG(sii, r, mask, val) \
45 W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val)))
52 #define R_SBREG(sii, sbr) sb_read_sbreg((sii), (sbr))
53 #define W_SBREG(sii, sbr, v) sb_write_sbreg((sii), (sbr), (v))
54 #define AND_SBREG(sii, sbr, v) W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) & (v)))
55 #define OR_SBREG(sii, sbr, v) W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v)))
58 sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr)
70 if (PCMCIA(sii)) {
71 INTR_OFF(sii, intr_val);
73 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
77 val = R_REG(sii->osh, sbr);
79 if (PCMCIA(sii)) {
81 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
82 INTR_RESTORE(sii, intr_val);
89 sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v)
102 if (PCMCIA(sii)) {
103 INTR_OFF(sii, intr_val);
105 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
109 if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) {
111 dummy = R_REG(sii->osh, sbr);
112 W_REG(sii->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
113 dummy = R_REG(sii->osh, sbr);
114 W_REG(sii->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
116 dummy = R_REG(sii->osh, sbr);
117 W_REG(sii->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
118 dummy = R_REG(sii->osh, sbr);
119 W_REG(sii->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
122 W_REG(sii->osh, sbr, v);
124 if (PCMCIA(sii)) {
126 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
127 INTR_RESTORE(sii, intr_val);
134 si_info_t *sii;
137 sii = SI_INFO(sih);
138 sb = REGS2SB(sii->curmap);
140 return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
146 si_info_t *sii;
151 sii = SI_INFO(sih);
153 INTR_OFF(sii, intr_val);
158 intflag = R_SBREG(sii, &sb->sbflagst);
160 INTR_RESTORE(sii, intr_val);
168 si_info_t *sii;
171 sii = SI_INFO(sih);
172 sb = REGS2SB(sii->curmap);
174 return R_SBREG(sii, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
180 si_info_t *sii;
184 sii = SI_INFO(sih);
185 sb = REGS2SB(sii->curmap);
191 W_SBREG(sii, &sb->sbintvec, vec);
196 BCMATTACHFN(_sb_coreidx)(si_info_t *sii, uint32 sba)
200 for (i = 0; i < sii->numcores; i ++)
201 if (sba == sii->coresba[i])
208 BCMATTACHFN(_sb_coresba)(si_info_t *sii)
213 switch (BUSTYPE(sii->pub.bustype)) {
215 sbconfig_t *sb = REGS2SB(sii->curmap);
216 sbaddr = sb_base(R_SBREG(sii, &sb->sbadmatch0));
221 sbaddr = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
226 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);
228 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);
230 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);
238 sbaddr = (uint32)(uintptr)sii->curmap;
253 si_info_t *sii;
256 sii = SI_INFO(sih);
257 sb = REGS2SB(sii->curmap);
259 return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
265 si_info_t *sii;
269 sii = SI_INFO(sih);
270 sb = REGS2SB(sii->curmap);
271 sbidh = R_SBREG(sii, &sb->sbidhigh);
280 si_info_t *sii;
284 sii = SI_INFO(sih);
285 sb = REGS2SB(sii->curmap);
290 w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
292 W_SBREG(sii, &sb->sbtmstatelow, w);
299 si_info_t *sii;
303 sii = SI_INFO(sih);
304 sb = REGS2SB(sii->curmap);
310 w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
312 W_SBREG(sii, &sb->sbtmstatelow, w);
318 return (R_SBREG(sii, &sb->sbtmstatelow) >> SBTML_SICF_SHIFT);
325 si_info_t *sii;
329 sii = SI_INFO(sih);
330 sb = REGS2SB(sii->curmap);
337 w = (R_SBREG(sii, &sb->sbtmstatehigh) & ~(mask << SBTMH_SISF_SHIFT)) |
339 W_SBREG(sii, &sb->sbtmstatehigh, w);
343 return (R_SBREG(sii, &sb->sbtmstatehigh) >> SBTMH_SISF_SHIFT);
349 si_info_t *sii;
352 sii = SI_INFO(sih);
353 sb = REGS2SB(sii->curmap);
355 return ((R_SBREG(sii, &sb->sbtmstatelow) &
377 si_info_t *sii;
379 sii = SI_INFO(sih);
388 if (BUSTYPE(sii->pub.bustype) == SI_BUS) {
392 if (!sii->regs[coreidx]) {
393 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
395 ASSERT(GOODREGS(sii->regs[coreidx]));
397 r = (uint32 *)((uchar *)sii->regs[coreidx] + regoff);
398 } else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
401 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
405 r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
406 } else if (sii->pub.buscoreidx == coreidx) {
411 if (SI_FAST(sii))
412 r = (uint32 *)((char *)sii->curmap +
415 r = (uint32 *)((char *)sii->curmap +
423 INTR_OFF(sii, intr_val);
426 origidx = si_coreidx(&sii->pub);
429 r = (uint32*) ((uchar*)sb_setcoreidx(&sii->pub, coreidx) + regoff);
436 w = (R_SBREG(sii, r) & ~mask) | val;
437 W_SBREG(sii, r, w);
439 w = (R_REG(sii->osh, r) & ~mask) | val;
440 W_REG(sii->osh, r, w);
446 w = R_SBREG(sii, r);
448 if ((CHIPID(sii->pub.chip) == BCM5354_CHIP_ID) &&
453 w = R_REG(sii->osh, r);
459 sb_setcoreidx(&sii->pub, origidx);
461 INTR_RESTORE(sii, intr_val);
476 BCMATTACHFN(_sb_scan)(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba, uint numcores)
491 for (i = 0, next = sii->numcores; i < numcores && next < SB_BUS_MAXCORES; i++, next++) {
492 sii->coresba[next] = sbba + (i * SI_CORE_SIZE);
495 if ((BUSTYPE(sii->pub.bustype) == SI_BUS) && (sii->coresba[next] == sba)) {
497 sii->regs[next] = regs;
501 sii->curmap = _sb_setcoreidx(sii, next);
502 sii->curidx = next;
504 sii->coreid[next] = sb_coreid(&sii->pub);
508 if (sii->coreid[next] == CC_CORE_ID) {
509 chipcregs_t *cc = (chipcregs_t *)sii->curmap;
510 uint32 ccrev = sb_corerev(&sii->pub);
514 numcores = (R_REG(sii->osh, &cc->chipid) & CID_CC_MASK) >>
518 uint chip = CHIPID(sii->pub.chip);
534 sii->pub.issim ? "QT" : ""));
537 else if (sii->coreid[next] == OCP_CORE_ID) {
538 sbconfig_t *sb = REGS2SB(sii->curmap);
539 uint32 nsbba = R_SBREG(sii, &sb->sbadmatch1);
542 sii->numcores = next + 1;
547 if (_sb_coreidx(sii, nsbba) != BADIDX)
550 nsbcc = (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >> 16;
551 nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc);
560 sii->numcores = i + ncc;
561 return sii->numcores;
568 si_info_t *sii;
572 sii = SI_INFO(sih);
573 sb = REGS2SB(sii->curmap);
575 sii->pub.socirev = (R_SBREG(sii, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
580 origsba = _sb_coresba(sii);
583 sii->numcores = _sb_scan(sii, origsba, regs, 0, SI_ENUM_BASE, 1);
594 si_info_t *sii;
596 sii = SI_INFO(sih);
598 if (coreidx >= sii->numcores)
605 ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
607 sii->curmap = _sb_setcoreidx(sii, coreidx);
608 sii->curidx = coreidx;
610 return (sii->curmap);
617 _sb_setcoreidx(si_info_t *sii, uint coreidx)
619 uint32 sbaddr = sii->coresba[coreidx];
622 switch (BUSTYPE(sii->pub.bustype)) {
625 if (!sii->regs[coreidx]) {
626 sii->regs[coreidx] = REG_MAP(sbaddr, SI_CORE_SIZE);
627 ASSERT(GOODREGS(sii->regs[coreidx]));
629 regs = sii->regs[coreidx];
634 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, sbaddr);
635 regs = sii->curmap;
640 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);
642 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);
644 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);
645 regs = sii->curmap;
652 if (!sii->regs[coreidx]) {
653 sii->regs[coreidx] = (void *)(uintptr)sbaddr;
654 ASSERT(GOODREGS(sii->regs[coreidx]));
656 regs = sii->regs[coreidx];
671 sb_admatch(si_info_t *sii, uint asidx)
676 sb = REGS2SB(sii->curmap);
707 si_info_t *sii;
710 sii = SI_INFO(sih);
711 sb = REGS2SB(sii->curmap);
714 return ((R_SBREG(sii, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT) + 1;
721 si_info_t *sii;
723 sii = SI_INFO(sih);
725 return (sb_base(R_SBREG(sii, sb_admatch(sii, asidx))));
732 si_info_t *sii;
734 sii = SI_INFO(sih);
736 return (sb_size(R_SBREG(sii, sb_admatch(sii, asidx))));
742 sb_serr_clear(si_info_t *sii)
749 INTR_OFF(sii, intr_val);
750 origidx = si_coreidx(&sii->pub);
752 for (i = 0; i < sii->numcores; i++) {
753 corereg = sb_setcoreidx(&sii->pub, i);
756 if ((R_SBREG(sii, &sb->sbtmstatehigh)) & SBTMH_SERR) {
757 AND_SBREG(sii, &sb->sbtmstatehigh, ~SBTMH_SERR);
759 sb_coreid(&sii->pub)));
764 sb_setcoreidx(&sii->pub, origidx);
765 INTR_RESTORE(sii, intr_val);
775 si_info_t *sii;
784 sii = SI_INFO(sih);
786 if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
790 stcmd = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_CMD, sizeof(uint32));
793 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_CFG_CMD, sizeof(uint32), stcmd);
797 stcmd = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_STATUS, sizeof(uint32));
800 sb_serr_clear(sii);
801 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_STATUS, sizeof(uint32), stcmd);
805 imstate = sb_corereg(sih, sii->pub.buscoreidx,
808 sb_corereg(sih, sii->pub.buscoreidx,
819 if (sii->pub.socirev == SONICS_2_2)
823 imerrlog = sb_corereg(sih, sii->pub.buscoreidx, SBIMERRLOG, 0, 0);
825 imerrloga = sb_corereg(sih, sii->pub.buscoreidx,
828 sb_corereg(sih, sii->pub.buscoreidx, SBIMERRLOG, ~0, 0);
836 } else if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) {
838 INTR_OFF(sii, intr_val);
845 imstate = R_SBREG(sii, &sb->sbimstate);
848 AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
852 tmstate = R_SBREG(sii, &sb->sbtmstatehigh);
856 sb_serr_clear(sii);
858 OR_SBREG(sii, &sb->sbtmstatelow, SBTML_INT_ACK);
859 AND_SBREG(sii, &sb->sbtmstatelow, ~SBTML_INT_ACK);
863 INTR_RESTORE(sii, intr_val);
882 si_info_t *sii;
886 sii = SI_INFO(sih);
888 origidx = sii->curidx;
891 INTR_OFF(sii, intr_val);
894 if (sii->pub.ccrev != NOREV) {
898 W_REG(sii->osh, &ccregs->broadcastaddress, SB_COMMIT);
899 W_REG(sii->osh, &ccregs->broadcastdata, 0x0);
900 } else if (PCI(sii)) {
904 W_REG(sii->osh, &pciregs->bcastaddr, SB_COMMIT);
905 W_REG(sii->osh, &pciregs->bcastdata, 0x0);
911 INTR_RESTORE(sii, intr_val);
917 si_info_t *sii;
921 sii = SI_INFO(sih);
923 ASSERT(GOODREGS(sii->curmap));
924 sb = REGS2SB(sii->curmap);
927 if (R_SBREG(sii, &sb->sbtmstatelow) & SBTML_RESET)
931 if ((R_SBREG(sii, &sb->sbtmstatelow) & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) == 0)
935 OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ);
936 dummy = R_SBREG(sii, &sb->sbtmstatelow);
938 SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
939 if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY)
942 if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) {
943 OR_SBREG(sii, &sb->sbimstate, SBIM_RJ);
944 dummy = R_SBREG(sii, &sb->sbimstate);
946 SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000);
950 W_SBREG(sii, &sb->sbtmstatelow,
953 dummy = R_SBREG(sii, &sb->sbtmstatelow);
957 if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT)
958 AND_SBREG(sii, &sb->sbimstate, ~SBIM_RJ);
962 W_SBREG(sii, &sb->sbtmstatelow, ((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET));
974 si_info_t *sii;
978 sii = SI_INFO(sih);
979 ASSERT(GOODREGS(sii->curmap));
980 sb = REGS2SB(sii->curmap);
992 W_SBREG(sii, &sb->sbtmstatelow,
995 dummy = R_SBREG(sii, &sb->sbtmstatelow);
998 if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR) {
999 W_SBREG(sii, &sb->sbtmstatehigh, 0);
1001 if ((dummy = R_SBREG(sii, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
1002 AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
1006 W_SBREG(sii, &sb->sbtmstatelow,
1008 dummy = R_SBREG(sii, &sb->sbtmstatelow);
1012 W_SBREG(sii, &sb->sbtmstatelow, ((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
1013 dummy = R_SBREG(sii, &sb->sbtmstatelow);
1044 si_info_t *sii;
1050 sii = SI_INFO(sih);
1057 switch (BUSTYPE(sii->pub.bustype)) {
1059 idx = sii->pub.buscoreidx;
1077 INTR_OFF(sii, intr_val);
1082 tmp = R_SBREG(sii, &sb->sbimconfiglow);
1084 W_SBREG(sii, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
1088 INTR_RESTORE(sii, intr_val);
1145 si_info_t *sii;
1149 sii = SI_INFO(sih);
1150 origidx = sii->curidx;
1152 INTR_OFF(sii, intr_val);
1154 for (i = 0; i < sii->numcores; i++) {
1157 bcm_bprintf(b, "core 0x%x: \n", sii->coreid[i]);
1159 if (sii->pub.socirev > SONICS_2_2)
1161 sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOG, 0, 0),
1162 sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOGA, 0, 0));
1166 R_SBREG(sii, &sb->sbtmstatelow), R_SBREG(sii, &sb->sbtmstatehigh),
1167 R_SBREG(sii, &sb->sbidhigh), R_SBREG(sii, &sb->sbimstate),
1168 R_SBREG(sii, &sb->sbimconfiglow), R_SBREG(sii, &sb->sbimconfighigh));
1172 INTR_RESTORE(sii, intr_val);