Lines Matching defs:to
7 * Permission to use, copy, modify, and/or distribute this software for any
361 * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
362 * switch back to the original core, and return the new value.
399 /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
467 /* Scan the enumeration space to find all cores starting from the given
468 * bus 'sbba'. Append coreid and other info to the lists in 'si'. 'sba'
483 SI_ERROR(("_sb_scan: bus 0x%08x at level %d is too deep to scan\n", sbba, bus));
500 /* change core to 'next' and read its coreid */
536 /* scan bridged SB(s) and add results to the end of the list */
564 /* scan the sb enumerated space to identify all cores */
587 * This function changes logical "focus" to the indicated core;
589 * Moreover, callers should keep interrupts off during switching out of and back to d11 core
613 /* This function changes the logical "focus" to the indicated core.
740 /* traverse all cores to find and clear source of serror */
893 /* switch over to chipcommon core if there is one, else use pci */
956 /* don't forget to clear the initiator reject bit */
983 * Must do the disable sequence first to work for arbitrary current core state.
1005 /* clear reset and allow it to propagate throughout the core */
1019 * The master core is defined to be the core in control
1020 * of the chip and so it issues accesses to non-memory
1023 * The routine uses the bus to decide who is the master:
1031 * timeouts so accesses to very slow devices like otp
1042 sb_set_initiator_to(si_t *sih, uint32 to, uint idx)
1052 if ((to & ~TO_MASK) != 0)
1084 W_SBREG(sii, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);