Lines Matching defs:sii
37 (sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
42 (sii->coreid[sii->curidx] == USB20H_CORE_ID))
116 ai_hwfixup(si_info_t *sii)
126 if (BUSTYPE(sii->pub.bustype) == SI_BUS &&
127 ((CHIPID(sii->pub.chip) == BCM4716_CHIP_ID) ||
128 (CHIPID(sii->pub.chip) == BCM4748_CHIP_ID))) {
131 ASSERT(sii->coreid[3] == MIPS74K_CORE_ID);
132 cpu = REG_MAP(sii->wrapba[3], SI_CORE_SIZE);
133 ASSERT(sii->coreid[5] == PCIE_CORE_ID);
134 pcie = REG_MAP(sii->wrapba[5], SI_CORE_SIZE);
135 ASSERT(sii->coreid[8] == I2S_CORE_ID);
136 i2s = REG_MAP(sii->wrapba[8], SI_CORE_SIZE);
137 if ((R_REG(sii->osh, &cpu->oobselina74) != 0x08060504) ||
138 (R_REG(sii->osh, &pcie->oobselina74) != 0x08060504) ||
139 (R_REG(sii->osh, &i2s->oobselouta30) != 0x88)) {
143 W_REG(sii->osh, &cpu->oobselina74, 0x07060504);
144 W_REG(sii->osh, &pcie->oobselina74, 0x07060504);
145 W_REG(sii->osh, &i2s->oobselouta30, 0x87);
203 si_info_t *sii = SI_INFO(sih);
204 uint i, coreid = sii->coreid[sii->curidx];
227 si_info_t *sii = SI_INFO(sih);
231 erombase = R_REG(sii->osh, &cc->eromptr);
240 sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
243 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
275 SI_VMSG(("Found END of erom after %d cores\n", sii->numcores));
276 ai_hwfixup(sii);
307 sii->oob_router = addrl;
314 idx = sii->numcores;
315 /* sii->eromptr[idx] = base; */
316 sii->cia[idx] = cia;
317 sii->cib[idx] = cib;
318 sii->coreid[idx] = remap_coreid(sih, cid);
348 sii->coresba[idx] = addrl;
349 sii->coresba_size[idx] = sizel;
356 sii->coresba2[idx] = addrl;
357 sii->coresba2_size[idx] = sizel;
388 sii->wrapba[idx] = addrl;
405 sii->wrapba[idx] = addrl;
413 sii->numcores++;
419 sii->numcores = 0;
429 si_info_t *sii = SI_INFO(sih);
430 uint32 addr = sii->coresba[coreidx];
431 uint32 wrap = sii->wrapba[coreidx];
434 if (coreidx >= sii->numcores)
441 ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
446 if (!sii->regs[coreidx]) {
447 sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
448 ASSERT(GOODREGS(sii->regs[coreidx]));
450 sii->curmap = regs = sii->regs[coreidx];
451 if (!sii->wrappers[coreidx]) {
452 sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
453 ASSERT(GOODREGS(sii->wrappers[coreidx]));
455 sii->curwrap = sii->wrappers[coreidx];
460 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr);
461 regs = sii->curmap;
463 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap);
468 sii->curmap = regs = (void *)((uintptr)addr);
469 sii->curwrap = (void *)((uintptr)wrap);
480 sii->curmap = regs;
481 sii->curidx = coreidx;
497 si_info_t *sii;
500 sii = SI_INFO(sih);
501 cidx = sii->curidx;
504 return sii->coresba[cidx];
506 return sii->coresba2[cidx];
518 si_info_t *sii;
521 sii = SI_INFO(sih);
522 cidx = sii->curidx;
525 return sii->coresba_size[cidx];
527 return sii->coresba2_size[cidx];
538 si_info_t *sii;
541 sii = SI_INFO(sih);
544 return sii->curidx;
548 return sii->curidx;
550 ai = sii->curwrap;
552 return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
563 si_info_t *sii = SI_INFO(sih);
564 uint32 *w = (uint32 *) sii->curwrap;
565 W_REG(sii->osh, w+(offset/4), val);
572 si_info_t *sii;
575 sii = SI_INFO(sih);
576 cia = sii->cia[sii->curidx];
583 si_info_t *sii;
586 sii = SI_INFO(sih);
587 cib = sii->cib[sii->curidx];
594 si_info_t *sii;
597 sii = SI_INFO(sih);
598 ai = sii->curwrap;
600 return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
601 ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
621 si_info_t *sii;
623 sii = SI_INFO(sih);
636 if (!sii->regs[coreidx]) {
637 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
639 ASSERT(GOODREGS(sii->regs[coreidx]));
641 r = (uint32 *)((uchar *)sii->regs[coreidx] + regoff);
645 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
649 r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
650 } else if (sii->pub.buscoreidx == coreidx) {
655 if (SI_FAST(sii))
656 r = (uint32 *)((char *)sii->curmap +
659 r = (uint32 *)((char *)sii->curmap +
667 INTR_OFF(sii, intr_val);
670 origidx = si_coreidx(&sii->pub);
673 r = (uint32*) ((uchar*) ai_setcoreidx(&sii->pub, coreidx) + regoff);
679 w = (R_REG(sii->osh, r) & ~mask) | val;
680 W_REG(sii->osh, r, w);
684 w = R_REG(sii->osh, r);
689 ai_setcoreidx(&sii->pub, origidx);
691 INTR_RESTORE(sii, intr_val);
700 si_info_t *sii;
704 sii = SI_INFO(sih);
706 ASSERT(GOODREGS(sii->curwrap));
707 ai = sii->curwrap;
710 if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
713 W_REG(sii->osh, &ai->ioctrl, bits);
714 dummy = R_REG(sii->osh, &ai->ioctrl);
717 W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
718 dummy = R_REG(sii->osh, &ai->resetctrl);
730 si_info_t *sii;
734 sii = SI_INFO(sih);
735 ASSERT(GOODREGS(sii->curwrap));
736 ai = sii->curwrap;
746 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
747 dummy = R_REG(sii->osh, &ai->ioctrl);
748 W_REG(sii->osh, &ai->resetctrl, 0);
751 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
752 dummy = R_REG(sii->osh, &ai->ioctrl);
760 si_info_t *sii;
764 sii = SI_INFO(sih);
777 ASSERT(GOODREGS(sii->curwrap));
778 ai = sii->curwrap;
783 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
784 W_REG(sii->osh, &ai->ioctrl, w);
791 si_info_t *sii;
795 sii = SI_INFO(sih);
807 ASSERT(GOODREGS(sii->curwrap));
808 ai = sii->curwrap;
813 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
814 W_REG(sii->osh, &ai->ioctrl, w);
817 return R_REG(sii->osh, &ai->ioctrl);
823 si_info_t *sii;
827 sii = SI_INFO(sih);
839 ASSERT(GOODREGS(sii->curwrap));
840 ai = sii->curwrap;
846 w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
847 W_REG(sii->osh, &ai->iostatus, w);
850 return R_REG(sii->osh, &ai->iostatus);
858 si_info_t *sii;
863 sii = SI_INFO(sih);
864 osh = sii->osh;
866 for (i = 0; i < sii->numcores; i++) {
867 si_setcoreidx(&sii->pub, i);
868 ai = sii->curwrap;
870 bcm_bprintf(b, "core 0x%x: \n", sii->coreid[i]);
908 if ((sih->chip == BCM4331_CHIP_ID) && (sii->coreid[i] == PCIE_CORE_ID)) {
910 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, 0x18103000);