Lines Matching refs:control_reg
159 u32 control_reg, clock, base_rate;
175 control_reg = le32_to_cpu(chip->comm_page->control_register);
176 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
193 if (control_reg & GML_SPDIF_PRO_MODE)
218 control_reg |= GML_DOUBLE_SPEED_MODE;
236 control_reg |= clock;
240 DE_ACT(("set_sample_rate: %d clock %d\n", rate, control_reg));
242 return write_control_reg(chip, control_reg, FALSE);
249 u32 control_reg, clocks_from_dsp;
252 control_reg = le32_to_cpu(chip->comm_page->control_register) &
265 control_reg |= GML_SPDIF_CLOCK;
267 control_reg &= ~GML_DOUBLE_SPEED_MODE;
271 control_reg |= GML_WORD_CLOCK;
273 control_reg |= GML_DOUBLE_SPEED_MODE;
275 control_reg &= ~GML_DOUBLE_SPEED_MODE;
281 control_reg |= GML_ADAT_CLOCK;
282 control_reg &= ~GML_DOUBLE_SPEED_MODE;
291 return write_control_reg(chip, control_reg, TRUE);
333 u32 control_reg;
370 control_reg = le32_to_cpu(chip->comm_page->control_register);
371 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
375 control_reg |= GML_SPDIF_OPTICAL_MODE;
381 control_reg |= GML_ADAT_MODE;
382 control_reg &= ~GML_DOUBLE_SPEED_MODE;
386 err = write_control_reg(chip, control_reg, TRUE);