Lines Matching refs:control_reg
124 u32 control_reg;
153 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
154 err = write_control_reg(chip, control_reg, TRUE);
164 u32 control_reg, clock;
181 control_reg = le32_to_cpu(chip->comm_page->control_register);
182 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
197 if (control_reg & GML_SPDIF_PRO_MODE)
221 control_reg |= clock;
227 return write_control_reg(chip, control_reg, FALSE);
234 u32 control_reg, clocks_from_dsp;
239 control_reg = le32_to_cpu(chip->comm_page->control_register) &
252 control_reg |= GML_SPDIF_CLOCK;
254 control_reg |= GML_DOUBLE_SPEED_MODE;
256 control_reg &= ~GML_DOUBLE_SPEED_MODE;
262 control_reg |= GML_ADAT_CLOCK;
263 control_reg &= ~GML_DOUBLE_SPEED_MODE;
267 control_reg |= GML_ESYNC_CLOCK;
268 control_reg &= ~GML_DOUBLE_SPEED_MODE;
272 control_reg |= GML_ESYNC_CLOCK | GML_DOUBLE_SPEED_MODE;
280 return write_control_reg(chip, control_reg, TRUE);
287 u32 control_reg;
316 control_reg = le32_to_cpu(chip->comm_page->control_register);
317 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
322 control_reg |= GML_SPDIF_OPTICAL_MODE;
327 control_reg |= GML_SPDIF_CDROM_MODE;
333 control_reg |= GML_ADAT_MODE;
334 control_reg &= ~GML_DOUBLE_SPEED_MODE;
338 err = write_control_reg(chip, control_reg, TRUE);