Lines Matching refs:devc
84 #define PORT(name) (devc->base+name)
133 static struct sscape_info *devc = &adev_info;
163 static unsigned char sscape_read(struct sscape_info *devc, int reg)
168 spin_lock_irqsave(&devc->lock,flags);
171 spin_unlock_irqrestore(&devc->lock,flags);
181 static void sscape_write(struct sscape_info *devc, int reg, int data)
185 spin_lock_irqsave(&devc->lock,flags);
187 spin_unlock_irqrestore(&devc->lock,flags);
190 static unsigned char sscape_pnp_read_codec(sscape_info* devc, unsigned char reg)
195 spin_lock_irqsave(&devc->lock,flags);
196 outb( reg, devc -> codec);
197 res = inb (devc -> codec + 1);
198 spin_unlock_irqrestore(&devc->lock,flags);
203 static void sscape_pnp_write_codec(sscape_info* devc, unsigned char reg, unsigned char data)
207 spin_lock_irqsave(&devc->lock,flags);
208 outb( reg, devc -> codec);
209 outb( data, devc -> codec + 1);
210 spin_unlock_irqrestore(&devc->lock,flags);
213 static void host_open(struct sscape_info *devc)
218 static void host_close(struct sscape_info *devc)
223 static int host_write(struct sscape_info *devc, unsigned char *data, int count)
228 spin_lock_irqsave(&devc->lock,flags);
241 spin_unlock_irqrestore(&devc->lock,flags);
246 spin_unlock_irqrestore(&devc->lock,flags);
250 static int host_read(struct sscape_info *devc)
256 spin_lock_irqsave(&devc->lock,flags);
267 spin_unlock_irqrestore(&devc->lock,flags);
271 spin_unlock_irqrestore(&devc->lock,flags);
277 static int host_command2(struct sscape_info *devc, int cmd, int parm1)
284 return host_write(devc, buf, 2);
287 static int host_command3(struct sscape_info *devc, int cmd, int parm1, int parm2)
294 return host_write(devc, buf, 3);
297 static void set_mt32(struct sscape_info *devc, int value)
299 host_open(devc);
300 host_command2(devc, CMD_SET_MT32, value ? 1 : 0);
301 if (host_read(devc) != CMD_ACK)
305 host_close(devc);
308 static void set_control(struct sscape_info *devc, int ctrl, int value)
310 host_open(devc);
311 host_command3(devc, CMD_SET_CONTROL, ctrl, value);
312 if (host_read(devc) != CMD_ACK)
316 host_close(devc);
319 static void do_dma(struct sscape_info *devc, int dma_chan, unsigned long buf, int blk_size, int mode)
328 audio_devs[devc->codec_audiodev]->flags &= ~DMA_AUTOMODE;
329 DMAbuf_start_dma(devc->codec_audiodev, buf, blk_size, mode);
330 audio_devs[devc->codec_audiodev]->flags |= DMA_AUTOMODE;
332 temp = devc->dma << 4; /* Setup DMA channel select bits */
333 if (devc->dma <= 3)
337 sscape_write(devc, GA_DMAA_REG, temp);
339 sscape_write(devc, GA_DMAA_REG, temp);
342 static int verify_mpu(struct sscape_info *devc)
358 if (inb(devc->base + HOST_CTRL) & 0x80)
361 if (inb(devc->base) != 0x00)
372 set_mt32(devc, 0);
373 if (!verify_mpu(devc))
381 struct sscape_info *devc = dev_info;
384 spin_lock_irqsave(&devc->lock,flags);
385 if (devc->dma_allocated)
388 devc->dma_allocated = 0;
390 spin_unlock_irqrestore(&devc->lock,flags);
398 static int sscape_download_boot(struct sscape_info *devc, unsigned char *block, int size, int flag)
412 spin_lock_irqsave(&devc->lock,flags);
413 codec_dma_bits = sscape_read(devc, GA_CDCFG_REG);
415 if (devc->dma_allocated == 0)
416 devc->dma_allocated = 1;
418 spin_unlock_irqrestore(&devc->lock,flags);
420 sscape_write(devc, GA_HMCTL_REG,
421 (temp = sscape_read(devc, GA_HMCTL_REG)) & 0x3f); /*Reset */
424 sscape_read(devc, GA_HMCTL_REG); /* Delay */
427 sscape_write(devc, GA_HMCTL_REG,
428 (temp = sscape_read(devc, GA_HMCTL_REG)) | 0x80);
433 if (audio_devs[devc->codec_audiodev]->dmap_out->raw_buf == NULL)
438 memcpy(audio_devs[devc->codec_audiodev]->dmap_out->raw_buf, block, size);
440 spin_lock_irqsave(&devc->lock,flags);
444 do_dma(devc, SSCAPE_DMA_A,
445 audio_devs[devc->codec_audiodev]->dmap_out->raw_buf_phys,
460 clear_dma_ff(devc->dma);
461 if ((resid = get_dma_residue(devc->dma)) == 0)
465 spin_unlock_irqrestore(&devc->lock,flags);
477 temp = sscape_read(devc, GA_HMCTL_REG);
479 sscape_write(devc, GA_HMCTL_REG, temp); /* Kickstart the board */
484 spin_lock_irqsave(&devc->lock,flags);
499 sscape_write(devc, GA_CDCFG_REG, codec_dma_bits);
501 spin_unlock_irqrestore(&devc->lock,flags);
507 spin_lock_irqsave(&devc->lock,flags);
516 spin_unlock_irqrestore(&devc->lock,flags);
523 set_control(devc, CTL_MASTER_VOL, 100);
524 set_control(devc, CTL_SYNTH_VOL, 100);
535 printk("I%d = %02x (new value)\n", i, sscape_read(devc, i));
548 if (!sscape_download_boot(devc, buf->data, buf->len, buf->flags))
653 release_region(devc->base, 2);
654 release_region(devc->base + 2, 6);
656 release_region(devc->codec, 2);
662 spin_lock_irqsave(&devc->lock,flags);
664 sscape_write(devc, 1, 0xf0); /* All interrupts enabled */
666 sscape_write(devc, 2, 0x20); /* DMA channel disabled */
668 sscape_write(devc, 3, 0x20); /* DMA channel disabled */
670 sscape_write(devc, 4, 0xf0 | (irq_bits << 2) | irq_bits);
672 sscape_write(devc, 5, (regs[5] & 0x3f) | (sscape_read(devc, 5) & 0xc0));
674 sscape_write(devc, 6, regs[6]);
675 sscape_write(devc, 7, regs[7]);
676 sscape_write(devc, 8, regs[8]);
678 sscape_write(devc, 9, (sscape_read(devc, 9) & 0xf0) | 0x08);
679 spin_unlock_irqrestore(&devc->lock,flags);
690 printk("I%d = %02x (new value)\n", i, sscape_read(devc, i));
707 sscape_write(devc, GA_INTENA_REG, 0x80); /* Master IRQ enable */
708 devc->ok = 1;
709 devc->failed = 0;
712 static int detect_ga(sscape_info * devc)
716 DDB(printk("Entered Soundscape detect_ga(%x)\n", devc->base));
748 if (sscape_read(devc, 0) & 0x0c)
750 DDB(printk("soundscape: Detect error D (%x)\n", sscape_read(devc, 0)));
753 if (sscape_read(devc, 1) & 0x0f)
758 if (sscape_read(devc, 5) & 0x0f)
766 static int sscape_read_host_ctrl(sscape_info* devc)
768 return host_read(devc);
771 static void sscape_write_host_ctrl2(sscape_info *devc, int a, int b)
773 host_command2(devc, a, b);
776 static int sscape_alloc_dma(sscape_info *devc)
783 if (devc->raw_buf != NULL) return 0; /* Already done */
784 dma_pagesize = (devc->dma < 4) ? (64 * 1024) : (128 * 1024);
785 devc->raw_buf = NULL;
786 devc->buffsize = 8192*4;
787 if (devc->buffsize > dma_pagesize) devc->buffsize = dma_pagesize;
794 while (start_addr == NULL && devc->buffsize > PAGE_SIZE) {
795 for (sz = 0, size = PAGE_SIZE; size < devc->buffsize; sz++, size <<= 1);
796 devc->buffsize = PAGE_SIZE * (1 << sz);
798 if (start_addr == NULL) devc->buffsize /= 2;
806 end_addr = start_addr + devc->buffsize - 1;
811 printk(KERN_ERR "sscape pnp: Got invalid address 0x%lx for %db DMA-buffer\n", (long) start_addr, devc->buffsize);
815 devc->raw_buf = start_addr;
816 devc->raw_buf_phys = virt_to_bus(start_addr);
823 static void sscape_free_dma(sscape_info *devc)
829 if (devc->raw_buf == NULL) return;
830 for (sz = 0, size = PAGE_SIZE; size < devc->buffsize; sz++, size <<= 1);
831 start_addr = (unsigned long) devc->raw_buf;
832 end_addr = start_addr + devc->buffsize;
837 free_pages((unsigned long) devc->raw_buf, sz);
838 devc->raw_buf = NULL;
858 static void sscape_pnp_start_dma(sscape_info* devc, int arg )
864 sscape_write(devc, reg, sscape_read( devc, reg) | 0x01);
865 sscape_write(devc, reg, sscape_read( devc, reg) & 0xFE);
868 static int sscape_pnp_wait_dma (sscape_info* devc, int arg )
880 d = sscape_read(devc, reg) & 1;
884 d = sscape_read(devc, reg) & 1;
888 static int sscape_pnp_alloc_dma(sscape_info* devc)
891 if (request_dma(devc -> dma, "sscape")) return 0;
893 if (!sscape_alloc_dma(devc)) {
894 free_dma(devc -> dma);
900 static void sscape_pnp_free_dma(sscape_info* devc)
902 sscape_free_dma( devc);
903 free_dma(devc -> dma );
907 static int sscape_pnp_upload_file(sscape_info* devc, char* fn)
915 sscape_write( devc, 9, sscape_read(devc, 9 ) & 0x3F );
916 sscape_write( devc, 2, (devc -> dma << 4) | 0x80 );
917 sscape_write( devc, 3, 0x20 );
918 sscape_write( devc, 9, sscape_read( devc, 9 ) | 0x80 );
926 spin_lock_irqsave(&devc->lock,flags);
928 if (len > devc -> buffsize) l = devc->buffsize;
931 memcpy(devc->raw_buf, dt, l); dt += l;
932 sscape_start_dma(devc->dma, devc->raw_buf_phys, l, 0x48);
933 sscape_pnp_start_dma ( devc, 0 );
934 if (sscape_pnp_wait_dma ( devc, 0 ) == 0) {
935 spin_unlock_irqrestore(&devc->lock,flags);
940 spin_unlock_irqrestore(&devc->lock,flags);
943 outb(0, devc -> base + 2);
944 outb(0, devc -> base);
946 sscape_write ( devc, 9, sscape_read( devc, 9 ) | 0x40);
953 x = inb( devc -> base + 3);
966 x = inb( devc -> base + 3);
976 sscape_write( devc, 2, devc->ic_type == IC_ODIE ? 0x70 : 0x40);
977 sscape_write( devc, 3, (devc -> dma << 4) + 0x80);
981 static void __init sscape_pnp_init_hw(sscape_info* devc)
991 if ( !sscape_pnp_alloc_dma(devc) ) {
997 if ( devc -> irq == valid_interrupts[i] )
999 if ( devc -> codec_irq == valid_interrupts[i] )
1003 sscape_write( devc, 5, 0x50);
1004 sscape_write( devc, 7, 0x2e);
1005 sscape_write( devc, 8, 0x00);
1007 sscape_write( devc, 2, devc->ic_type == IC_ODIE ? 0x70 : 0x40);
1008 sscape_write( devc, 3, ( devc -> dma << 4) | 0x80);
1010 sscape_write (devc, 4, 0xF0 | (midi_irq<<2) | midi_irq);
1012 i = 0x10; //sscape_read(devc, 9) & (devc->ic_type == IC_ODIE ? 0xf0 : 0xc0);
1015 sscape_write (devc, 9, i);
1016 sscape_write (devc, 6, 0x80);
1017 sscape_write (devc, 1, 0x80);
1019 if (devc -> codec_type == 2) {
1020 sscape_pnp_write_codec( devc, 0x0C, 0x50);
1021 sscape_pnp_write_codec( devc, 0x10, sscape_pnp_read_codec( devc, 0x10) & 0x3F);
1022 sscape_pnp_write_codec( devc, 0x11, sscape_pnp_read_codec( devc, 0x11) | 0xC0);
1023 sscape_pnp_write_codec( devc, 29, 0x20);
1026 if (sscape_pnp_upload_file(devc, "/sndscape/scope.cod") == 0 ) {
1028 sscape_pnp_free_dma(devc);
1032 i = sscape_read_host_ctrl( devc );
1036 sscape_pnp_free_dma(devc);
1039 if ( i & 0x10 ) sscape_write( devc, 7, 0x2F);
1041 if (sscape_pnp_upload_file( devc, code_file_name) == 0) {
1043 sscape_pnp_free_dma(devc);
1047 if (devc->ic_type != IC_ODIE) {
1048 sscape_pnp_write_codec( devc, 10, (sscape_pnp_read_codec(devc, 10) & 0x7f) |
1051 sscape_write_host_ctrl2( devc, 0x84, 0x64 ); /* MIDI volume */
1052 sscape_write_host_ctrl2( devc, 0x86, 0x64 ); /* MIDI volume?? */
1053 sscape_write_host_ctrl2( devc, 0x8A, sscape_ext_midi);
1055 sscape_pnp_write_codec ( devc, 6, 0x3f ); //WAV_VOL
1056 sscape_pnp_write_codec ( devc, 7, 0x3f ); //WAV_VOL
1057 sscape_pnp_write_codec ( devc, 2, 0x1F ); //WD_CDXVOLL
1058 sscape_pnp_write_codec ( devc, 3, 0x1F ); //WD_CDXVOLR
1060 if (devc -> codec_type == 1) {
1061 sscape_pnp_write_codec ( devc, 4, 0x1F );
1062 sscape_pnp_write_codec ( devc, 5, 0x1F );
1063 sscape_write_host_ctrl2( devc, 0x88, sscape_mic_enable);
1066 sscape_pnp_write_codec ( devc, 0x10, 0x1F << 1);
1067 sscape_pnp_write_codec ( devc, 0x11, 0xC0 | (0x1F << 1));
1069 t = sscape_pnp_read_codec( devc, 0x00) & 0xDF;
1072 sscape_pnp_write_codec ( devc, 0x00, t);
1073 t = sscape_pnp_read_codec( devc, 0x01) & 0xDF;
1076 sscape_pnp_write_codec ( devc, 0x01, t);
1077 sscape_pnp_write_codec ( devc, 0x40 | 29 , 0x20);
1078 outb(0, devc -> codec);
1080 if (devc -> ic_type == IC_OPUS ) {
1081 int i = sscape_read( devc, 9 );
1082 sscape_write( devc, 9, i | 3 );
1083 sscape_write( devc, 3, 0x40);
1089 sscape_write( devc, 3, (devc -> dma << 4) | 0x80);
1090 sscape_write( devc, 9, i );
1093 host_close ( devc );
1094 sscape_pnp_free_dma(devc);
1097 static int __init detect_sscape_pnp(sscape_info* devc)
1102 DDB(printk("Entered detect_sscape_pnp(%x)\n", devc->base));
1104 if (!request_region(devc->codec, 2, "sscape codec")) {
1105 printk(KERN_ERR "detect_sscape_pnp: port %x is not free\n", devc->codec);
1109 if ((inb(devc->base + 2) & 0x78) != 0)
1112 d = inb ( devc -> base + 4) & 0xF0;
1117 devc->codec_type = 1;
1118 devc->ic_type = IC_ODIE;
1120 devc->codec_type = 2;
1121 devc->ic_type = IC_OPUS;
1123 devc->codec_type = 2;
1124 devc->ic_type = IC_ODIE;
1130 outb(0xFA, devc -> base+4);
1131 if ((inb( devc -> base+4) & 0x9F) != 0x0A)
1133 outb(0xFE, devc -> base+4);
1134 if ( (inb(devc -> base+4) & 0x9F) != 0x0E)
1136 if ( (inb(devc -> base+5) & 0x9F) != 0x0E)
1139 if (devc->codec_type == 2) {
1140 if (devc->codec != devc->base + 8) {
1144 d = 0x10 | (sscape_read(devc, 9) & 0xCF);
1145 sscape_write(devc, 9, d);
1146 sscape_write(devc, 6, 0x80);
1151 d = (sscape_read(devc, 9) & 0x3F) | 0xC0;
1152 sscape_write(devc, 9, d);
1155 if ( !(inb(devc -> codec) & 0x80) ) break;
1157 d = inb(devc -> codec);
1160 if ( inb(devc -> codec + 2) == 0xFF)
1163 sscape_write(devc, 9, sscape_read(devc, 9) & 0x3F );
1165 d = inb(devc -> codec) & 0x80;
1175 sscape_write( devc, 9, 0xC0 | (sscape_read(devc, 9) & 0x3F) );
1178 if ( !(inb(devc -> codec) & 0x80))
1181 sscape_pnp_init_hw(devc);
1185 if (devc->codec_irq == valid_interrupts[i]) {
1190 sscape_write(devc, GA_INTENA_REG, 0x00);
1191 sscape_write(devc, GA_DMACFG_REG, 0x50);
1192 sscape_write(devc, GA_DMAA_REG, 0x70);
1193 sscape_write(devc, GA_DMAB_REG, 0x20);
1194 sscape_write(devc, GA_INTCFG_REG, 0xf0);
1195 sscape_write(devc, GA_CDCFG_REG, 0x89 | (devc->dma << 4) | (irq_bits << 1));
1197 sscape_pnp_write_codec( devc, 0, sscape_pnp_read_codec( devc, 0) | 0x20);
1198 sscape_pnp_write_codec( devc, 0, sscape_pnp_read_codec( devc, 1) | 0x20);
1202 release_region(devc->codec, 2);
1208 devc->base = hw_config->io_base;
1209 devc->irq = hw_config->irq;
1210 devc->dma = hw_config->dma;
1211 devc->osp = hw_config->osp;
1222 printk("I%d = %02x (old value)\n", i, sscape_read(devc, i));
1225 devc->failed = 1;
1227 sscape_ports = request_region(devc->base, 2, "mpu401");
1231 if (!request_region(devc->base + 2, 6, "SoundScape")) {
1232 release_region(devc->base, 2);
1236 if (!detect_ga(devc)) {
1237 if (detect_sscape_pnp(devc))
1239 release_region(devc->base, 2);
1240 release_region(devc->base + 2, 6);
1249 if (!((tmp = sscape_read(devc, GA_HMCTL_REG)) & 0xc0))
1251 sscape_write(devc, GA_HMCTL_REG, tmp | 0x80);
1253 inb(devc->base + ODIE_ADDR);
1265 if (devc->failed)
1270 if (devc->ok == 0)
1309 sscape_write(devc, GA_DMACFG_REG, 0x50);
1314 sscape_write(devc, GA_DMAB_REG, 0x20);
1319 sscape_write(devc, GA_CDCFG_REG, 0x89 | (hw_config->dma << 4) | (irq_bits << 1));
1322 if (hw_config->irq == devc->irq)
1332 devc->osp,
1339 devc->codec_audiodev = hw_config->slots[0];
1340 devc->my_audiodev = hw_config->slots[0];
1355 printk("I%d = %02x\n", i, sscape_read(devc, i));
1363 release_region(devc->base + 2, 6);
1366 release_region(devc->codec, 2);
1373 devc->dma,
1374 devc->dma,
1411 devc->codec = cfg.io_base;
1412 devc->codec_irq = cfg.irq;
1413 devc->codec_type = 0;
1414 devc->ic_type = 0;
1415 devc->raw_buf = NULL;
1416 spin_lock_init(&devc->lock);