Lines Matching refs:ad_write
232 static void ad_write(ad1848_info * devc, int reg, int data)
413 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
414 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
438 ad_write(devc, devc->mix_devices[i][j].recreg, val);
524 ad_write(devc, regoffs, val);
527 ad_write(devc, muteregoffs, muteval);
657 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
659 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
666 ad_write(devc, 16, 0x60);
690 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
692 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
1066 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1067 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1109 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1110 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1114 ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1115 ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1148 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1149 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1156 ad_write(devc, 16, tmp | 0x30);
1159 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1161 ad_write(devc, 8, fs);
1175 ad_write(devc, 16, tmp & ~0x30);
1217 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1218 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1223 ad_write(devc, 16, tmp | 0x30);
1226 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1235 ad_write(devc, 28, fs);
1258 ad_write(devc, 8, tmp);
1275 ad_write(devc, 8, fs);
1288 ad_write(devc, 16, tmp & ~0x30);
1345 ad_write(devc, 9, ad_read(devc, 9) & ~0x02); /* Stop capture */
1380 ad_write(devc, 9, ad_read(devc, 9) & ~0x01); /* Stop playback */
1425 ad_write(devc, 9, tmp);
1476 ad_write(devc, i, init_values[i]);
1485 ad_write(devc, 12, ad_read(devc, 12) | 0x50);
1487 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1490 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1494 ad_write(devc, i, init_values[i]);
1497 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1502 ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */
1504 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1507 ad_write(devc, 27, ad_read(devc, 27) | 0x08); /* Alternate freq select enabled */
1511 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1512 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1513 ad_write(devc, 17, 0xc2); /* Alternate feature enable */
1519 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1521 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1636 ad_write(devc, 0, 0xaa);
1637 ad_write(devc, 1, 0x45); /* 0x55 with bit 0x10 clear */
1650 ad_write(devc, 0, 0x45);
1651 ad_write(devc, 1, 0xaa);
1671 ad_write(devc, 12, (~tmp) & 0x0f);
1699 ad_write(devc, 12, 0); /* Mode2=disabled */
1722 ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */
1745 ad_write(devc, 16, 0); /* Set I16 to known value */
1747 ad_write(devc, 0, 0x45);
1750 ad_write(devc, 0, 0xaa);
1763 ad_write(devc, 25, ~tmp1); /* Invert all bits */
1797 ad_write(devc, 23, ~tmp);
1815 ad_write(devc, 12, ad_read(devc, 12) & ~0x40); /* Mode2 off */
1817 ad_write(devc, 23, tmp); /* Restore */
1825 ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1826 ad_write(devc, 23, 0x9c); /* select extended register 25 */
1828 ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1902 ad_write(devc, 25, tmp1); /* Restore bits */
2045 ad_write(devc, 21, 0x00); /* Timer MSB */
2046 ad_write(devc, 20, 0x10); /* Timer LSB */
2048 ad_write(devc, 16, tmp | 0x40); /* Enable timer */
2050 ad_write(devc, 16, tmp & ~0x40); /* Disable timer */
2114 ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
2242 ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat); /* Selective ack */
2736 ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */
2737 ad_write(devc, 20, divider & 0xff); /* Set lower bits */
2738 ad_write(devc, 16, ad_read(devc, 16) | 0x40); /* Start the timer */
2762 ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
2776 ad_write(devc, 16, ad_read(devc, 16) | 0x40);