Lines Matching refs:snd_uda1341_cfg_write
237 static int snd_uda1341_cfg_write(struct l3_client *clnt, unsigned short what,
839 return snd_uda1341_cfg_write(clnt, cmd, (int) arg, FLUSH);
851 snd_uda1341_cfg_write(clnt, CMD_RESET, 0, REGS_ONLY);
852 snd_uda1341_cfg_write(clnt, CMD_FS, F256, FLUSH); // unknown state after reset
853 snd_uda1341_cfg_write(clnt, CMD_FORMAT, LSB16, FLUSH); // unknown state after reset
854 snd_uda1341_cfg_write(clnt, CMD_OGAIN, ON, FLUSH); // default off after reset
855 snd_uda1341_cfg_write(clnt, CMD_IGAIN, ON, FLUSH); // default off after reset
856 snd_uda1341_cfg_write(clnt, CMD_DAC, ON, FLUSH); // ??? default value after reset
857 snd_uda1341_cfg_write(clnt, CMD_ADC, ON, FLUSH); // ??? default value after reset
858 snd_uda1341_cfg_write(clnt, CMD_VOLUME, 20, FLUSH); // default 0dB after reset
859 snd_uda1341_cfg_write(clnt, CMD_BASS, 0, REGS_ONLY); // default value after reset
860 snd_uda1341_cfg_write(clnt, CMD_TREBBLE, 0, REGS_ONLY); // default value after reset
861 snd_uda1341_cfg_write(clnt, CMD_PEAK, AFTER, REGS_ONLY);// default value after reset
862 snd_uda1341_cfg_write(clnt, CMD_DEEMP, NONE, REGS_ONLY);// default value after reset
864 snd_uda1341_cfg_write(clnt, CMD_MUTE, OFF, REGS_ONLY); // default value after reset
865 snd_uda1341_cfg_write(clnt, CMD_FILTER, MAX, FLUSH); // defaul flat after reset
866 snd_uda1341_cfg_write(clnt, CMD_CH1, 31, FLUSH); // default value after reset
867 snd_uda1341_cfg_write(clnt, CMD_CH2, 4, FLUSH); // default value after reset
868 snd_uda1341_cfg_write(clnt, CMD_MIC, 4, FLUSH); // default 0dB after reset
869 snd_uda1341_cfg_write(clnt, CMD_MIXER, MIXER, FLUSH); // default doub.dif.mode
870 snd_uda1341_cfg_write(clnt, CMD_AGC, OFF, FLUSH); // default value after reset
871 snd_uda1341_cfg_write(clnt, CMD_IG, 0, FLUSH); // unknown state after reset
872 snd_uda1341_cfg_write(clnt, CMD_AGC_TIME, 0, FLUSH); // default value after reset
873 snd_uda1341_cfg_write(clnt, CMD_AGC_LEVEL, 0, FLUSH); // default value after reset