Lines Matching refs:and
42 * trap entry and to process TSB misses. These cannot be in the
43 * per_cpu() area as we really need to lock them into the TLB and
47 * This is padded out and aligned to 64-bytes to avoid false sharing
56 /* D-cache line 1: Basic thread information, cpu and device mondo queues */
62 /* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
68 /* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
71 /* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */
77 /* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */
144 and REG, 0x1f, REG; \
152 and REG, 0x3ff, REG; \
157 and REG, 0x1f, REG; \
196 * area base of the current processor into DEST. REG1, REG2, and REG3 are
200 * reason is that traps can happen during execution, and return from