Lines Matching refs:base
226 #define DCRN_UIC_SR(base) (base + 0x0)
227 #define DCRN_UIC_ER(base) (base + 0x2)
228 #define DCRN_UIC_CR(base) (base + 0x3)
229 #define DCRN_UIC_PR(base) (base + 0x4)
230 #define DCRN_UIC_TR(base) (base + 0x5)
231 #define DCRN_UIC_MSR(base) (base + 0x6)
232 #define DCRN_UIC_VR(base) (base + 0x7)
233 #define DCRN_UIC_VCR(base) (base + 0x8)
248 #define DCRN_MALCR(base) (base + 0x0) /* Configuration */
249 #define DCRN_MALESR(base) (base + 0x1) /* Error Status */
250 #define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */
251 #define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */
252 #define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */
253 #define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */
254 #define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */
255 #define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */
256 #define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */
257 #define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */
258 #define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */
259 #define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */
260 #define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */
261 #define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */
262 #define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */
263 #define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */
264 #define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */
265 #define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */
266 #define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */
269 #define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
270 #define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
271 #define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
272 #define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
273 #define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
274 #define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
275 #define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
276 #define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */