Lines Matching refs:x4
73 #define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4)
77 #define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4)
91 #define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4)
95 #define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4)
105 #define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */
108 #define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */
118 #define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */
121 #define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */
196 #define DCRN_MALTXCASR(base) ((base) + 0x4) /* TX Channel Active Set Register */
274 #define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4)
280 #define DCRN_UIC_PR(base) (base + 0x4)