Lines Matching refs:IOASIC_SLOT_SIZE
21 #define IOASIC_SLOT_SIZE 0x00040000
26 #define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE) /* system board ROM */
27 #define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
28 #define IOASIC_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
29 #define IOASIC_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
30 #define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */
31 #define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE) /* VDAC (maxine) */
32 #define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */
33 #define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE) /* VDAC (maxine) */
34 #define IOASIC_TOY (8*IOASIC_SLOT_SIZE) /* RTC */
35 #define IOASIC_ISDN (9*IOASIC_SLOT_SIZE) /* ISDN (maxine) */
36 #define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE) /* bus error address (3max+) */
37 #define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE) /* ECC syndrome (3max+) */
38 #define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE) /* ACCESS.bus (maxine) */
39 #define IOASIC_MCR (11*IOASIC_SLOT_SIZE) /* memory control (3max+) */
40 #define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */
41 #define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
42 #define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */
43 #define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */
44 #define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */