Lines Matching defs:VRC5477_IRQ_BASE
258 #define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
264 #define VRC5477_IRQ_CPCE (0 + VRC5477_IRQ_BASE) /* cpu parity error */
265 #define VRC5477_IRQ_CNTD (1 + VRC5477_IRQ_BASE) /* cpu no target */
266 #define VRC5477_IRQ_I2C (2 + VRC5477_IRQ_BASE) /* I2C */
267 #define VRC5477_IRQ_DMA (3 + VRC5477_IRQ_BASE) /* DMA */
268 #define VRC5477_IRQ_UART0 (4 + VRC5477_IRQ_BASE)
269 #define VRC5477_IRQ_WDOG (5 + VRC5477_IRQ_BASE) /* watchdog timer */
270 #define VRC5477_IRQ_SPT1 (6 + VRC5477_IRQ_BASE) /* special purpose timer 1 */
271 #define VRC5477_IRQ_LBRT (7 + VRC5477_IRQ_BASE) /* local bus read timeout */
272 #define VRC5477_IRQ_INTA (8 + VRC5477_IRQ_BASE) /* PCI INT #A */
273 #define VRC5477_IRQ_INTB (9 + VRC5477_IRQ_BASE) /* PCI INT #B */
274 #define VRC5477_IRQ_INTC (10 + VRC5477_IRQ_BASE) /* PCI INT #C */
275 #define VRC5477_IRQ_INTD (11 + VRC5477_IRQ_BASE) /* PCI INT #D */
276 #define VRC5477_IRQ_INTE (12 + VRC5477_IRQ_BASE) /* PCI INT #E */
277 #define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved */
278 #define VRC5477_IRQ_PCIS (14 + VRC5477_IRQ_BASE) /* PCI SERR # */
279 #define VRC5477_IRQ_PCI (15 + VRC5477_IRQ_BASE) /* PCI internal error */
280 #define VRC5477_IRQ_IOPCI_INTA (16 + VRC5477_IRQ_BASE) /* USB-H */
281 #define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */
282 #define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */
283 #define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */
284 #define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
285 #define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */
286 #define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */
287 #define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */
288 #define VRC5477_IRQ_GPT2 (24 + VRC5477_IRQ_BASE) /* general purpose timer 2 */
289 #define VRC5477_IRQ_GPT3 (25 + VRC5477_IRQ_BASE) /* general purpose timer 3 */
290 #define VRC5477_IRQ_GPIO (26 + VRC5477_IRQ_BASE)
291 #define VRC5477_IRQ_SIO0 (27 + VRC5477_IRQ_BASE)
292 #define VRC5477_IRQ_SIO1 (28 + VRC5477_IRQ_BASE)
293 #define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE) /* reserved */
294 #define VRC5477_IRQ_IOPCISERR (30 + VRC5477_IRQ_BASE) /* IO PCI SERR # */
295 #define VRC5477_IRQ_IOPCI (31 + VRC5477_IRQ_BASE)
321 #define VRC5477_I8259_CASCADE (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE)