Lines Matching refs:M32R_ICU_OFFSET
212 #define M32R_ICU_OFFSET (0x000FF000+M32R_SFR_OFFSET)
214 #define M32R_ICU_ISTS_PORTL (0x004+M32R_ICU_OFFSET)
215 #define M32R_ICU_IREQ0_PORTL (0x008+M32R_ICU_OFFSET)
216 #define M32R_ICU_IREQ1_PORTL (0x00C+M32R_ICU_OFFSET)
217 #define M32R_ICU_SBICR_PORTL (0x018+M32R_ICU_OFFSET)
218 #define M32R_ICU_IMASK_PORTL (0x01C+M32R_ICU_OFFSET)
219 #define M32R_ICU_CR1_PORTL (0x200+M32R_ICU_OFFSET) /* INT0 */
220 #define M32R_ICU_CR2_PORTL (0x204+M32R_ICU_OFFSET) /* INT1 */
221 #define M32R_ICU_CR3_PORTL (0x208+M32R_ICU_OFFSET) /* INT2 */
222 #define M32R_ICU_CR4_PORTL (0x20C+M32R_ICU_OFFSET) /* INT3 */
223 #define M32R_ICU_CR5_PORTL (0x210+M32R_ICU_OFFSET) /* INT4 */
224 #define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */
225 #define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */
226 #define M32R_ICU_CR8_PORTL (0x218+M32R_ICU_OFFSET) /* INT7 */
227 #define M32R_ICU_CR32_PORTL (0x27C+M32R_ICU_OFFSET) /* SIO0 RX */
228 #define M32R_ICU_CR33_PORTL (0x280+M32R_ICU_OFFSET) /* SIO0 TX */
229 #define M32R_ICU_CR40_PORTL (0x29C+M32R_ICU_OFFSET) /* DMAC0 */
230 #define M32R_ICU_CR41_PORTL (0x2A0+M32R_ICU_OFFSET) /* DMAC1 */
231 #define M32R_ICU_CR48_PORTL (0x2BC+M32R_ICU_OFFSET) /* MFT0 */
232 #define M32R_ICU_CR49_PORTL (0x2C0+M32R_ICU_OFFSET) /* MFT1 */
233 #define M32R_ICU_CR50_PORTL (0x2C4+M32R_ICU_OFFSET) /* MFT2 */
234 #define M32R_ICU_CR51_PORTL (0x2C8+M32R_ICU_OFFSET) /* MFT3 */
235 #define M32R_ICU_CR52_PORTL (0x2CC+M32R_ICU_OFFSET) /* MFT4 */
236 #define M32R_ICU_CR53_PORTL (0x2D0+M32R_ICU_OFFSET) /* MFT5 */
237 #define M32R_ICU_IPICR0_PORTL (0x2DC+M32R_ICU_OFFSET) /* IPI0 */
238 #define M32R_ICU_IPICR1_PORTL (0x2E0+M32R_ICU_OFFSET) /* IPI1 */
239 #define M32R_ICU_IPICR2_PORTL (0x2E4+M32R_ICU_OFFSET) /* IPI2 */
240 #define M32R_ICU_IPICR3_PORTL (0x2E8+M32R_ICU_OFFSET) /* IPI3 */
241 #define M32R_ICU_IPICR4_PORTL (0x2EC+M32R_ICU_OFFSET) /* IPI4 */
242 #define M32R_ICU_IPICR5_PORTL (0x2F0+M32R_ICU_OFFSET) /* IPI5 */
243 #define M32R_ICU_IPICR6_PORTL (0x2F4+M32R_ICU_OFFSET) /* IPI6 */
244 #define M32R_ICU_IPICR7_PORTL (0x2FC+M32R_ICU_OFFSET) /* IPI7 */