Lines Matching refs:MK_BMSK_
41 #define MK_BMSK_(x) (1<<x)
155 #define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
157 #define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
159 #define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
161 #define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
163 #define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
165 #define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
167 #define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
169 #define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
171 #define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
173 #define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
175 #define ASTAT_V MK_BMSK_(ASTAT_V_P)
177 #define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
204 #define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
205 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
206 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
207 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
208 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
209 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
213 #define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
216 #define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
217 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
218 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
219 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
220 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
249 #define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
251 #define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
253 #define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
538 #define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
539 #define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
540 #define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
541 #define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
542 #define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
543 #define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
544 #define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
545 #define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
546 #define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
547 #define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
548 #define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
549 #define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
550 #define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
551 #define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
552 #define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
553 #define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */