Lines Matching refs:IVG_BASE
143 #define IVG_BASE 7
145 #define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
146 #define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
148 #define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
149 #define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
150 #define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
152 #define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
153 #define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
154 #define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
155 #define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
156 #define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
157 #define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */
159 #define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
162 #define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
164 #define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
165 #define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
166 #define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
167 #define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
168 #define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
169 #define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
170 #define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
171 #define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
172 #define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
173 #define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
175 #define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
177 #define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
179 #define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
181 #define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
183 #define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
185 #define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
187 #define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
189 #define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
190 #define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
191 #define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
192 #define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
193 #define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
195 #define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
196 #define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
197 #define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
198 #define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
199 #define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
200 #define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
201 #define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
202 #define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
203 #define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
204 #define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
205 #define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
206 #define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
208 #define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
210 #define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
212 #define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
213 #define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
214 #define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
215 #define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
217 #define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
220 #define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */
224 #define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
226 #define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */
229 #define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
231 #define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */
234 #define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */
236 #define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
237 #define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
238 #define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
239 #define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */