Lines Matching refs:x4
1524 #define IRQ_EPPI0_ERR 0x4 /* EPPI0 Error */
1585 #define IRQ_DMA19 0x4 /* DMA Channel 19 */
1658 #define IRQ_DMA17 0x4 /* DMA Channel 17 */
1731 #define DFETCH 0x4 /* DMA Descriptor Fetch */
1891 #define DEB3_ERROR 0x4 /* DEB3 Error */
1912 #define PFTCHSRESET 0x4 /* DDR prefetch reset */
2019 #define B2WCENABLE 0x4 /* Bank 2 write count enable */
2069 #define CB2WCOUNT 0x4 /* Clear write count 2 */
2118 #define Px2 0x4 /* GPIO 2 */
2173 #define IB2 0x4 /* Interrupt Bit 2 */
2205 #define PULSE_HI 0x4 /* Pulse Polarity */
2229 #define TIMEN2 0x4 /* Timer 2 Enable */
2248 #define TIMDIS2 0x4 /* Timer 2 Disable */
2267 #define TIMIL2 0x4 /* Timer 2 Interrupt */
2344 #define DCIE 0x4 /* Down count Interrupt Enable */
2369 #define DCII 0x4 /* Down count Interrupt Identifier */
2413 #define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */
2432 #define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */
2528 #define SECURE2 0x4 /* SECURE 2 */
2536 #define NMI 0x4 /* Non Maskable Interrupt */
2571 #define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
2625 #define PG_WR_STAT 0x4 /* Page Write Pending */
2638 #define WB_EDGE 0x4 /* Write Buffer Edge Detect */
2651 #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
2696 #define ABO 0x4 /* Auto Bus On */
2713 #define EP 0x4 /* CAN Error Passive Mode */
2733 #define DTO 0x4 /* Disable CANTX Output Pin */
2764 #define GIRQ 0x4 /* Global Interrupt Request Status */
2777 #define EPIM 0x4 /* Error Passive Interrupt Mask */
2800 #define EPIS 0x4 /* Error Passive Interrupt Status */
2823 #define EPIF 0x4 /* Error Passive Interrupt Flag */
2883 #define ACKE 0x4 /* Acknowledge Error */
2957 #define MC2 0x4 /* Mailbox 2 Enable */
2992 #define MC18 0x4 /* Mailbox 18 Enable */
3027 #define MD2 0x4 /* Mailbox 2 Receive Enable */
3062 #define MD18 0x4 /* Mailbox 18 Receive Enable */
3097 #define RMP2 0x4 /* Mailbox 2 Receive Message Pending */
3132 #define RMP18 0x4 /* Mailbox 18 Receive Message Pending */
3167 #define RML2 0x4 /* Mailbox 2 Receive Message Lost */
3202 #define RML18 0x4 /* Mailbox 18 Receive Message Lost */
3237 #define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
3272 #define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
3307 #define TRS2 0x4 /* Mailbox 2 Transmit Request Set */
3342 #define TRS18 0x4 /* Mailbox 18 Transmit Request Set */
3377 #define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */
3412 #define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */
3447 #define AA2 0x4 /* Mailbox 2 Abort Acknowledge */
3482 #define AA18 0x4 /* Mailbox 18 Abort Acknowledge */
3517 #define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */
3552 #define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */
3587 #define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */
3622 #define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */
3657 #define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */
3692 #define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */
3727 #define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */
3762 #define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */
3797 #define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */
3832 #define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */
3867 #define LTERR_OVR 0x4 /* Line Track Overflow */
3973 #define SZ 0x4 /* Send Zero */
3981 #define FLS2 0x4 /* Slave Select Enable 2 */
4002 #define TXE 0x4 /* Transmission Error */
4044 #define STDVAL 0x4 /* Slave Transmit Data Valid */
4066 #define MDIR 0x4 /* Master Transfer Direction */
4090 #define ANAK 0x4 /* Address Not Acknowledged */
4111 #define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
4127 #define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
4146 #define SERR 0x4 /* Slave Transfer Error */
4247 #define ROVF 0x4 /* Sticky Receive Overflow Status */
4268 #define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
4278 #define STB 0x4 /* Stop Bits */
4295 #define RFIT 0x4 /* Receive FIFO IRQ Threshold */
4314 #define PE 0x4 /* Parity Error */
4342 #define ELSI_S 0x4 /* Enable Receive Status Interrupt */
4359 #define ELSI_C 0x4 /* Enable Receive Status Interrupt */
4376 #define TPOLC 0x4 /* IrDA TX Polarity Change */