Lines Matching refs:x4
905 #define OVR_B_EN 0x4 /* Overlay B Enable */
967 #define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
1014 #define DATA_SIZE 0x4 /* Data Size */
1037 #define FIFOEMPTY 0x4 /* FIFO Empty */
1137 #define DTX_MODE 0x4 /* Data Transfer Mode */
1149 #define CMD_TIMEOUT 0x4 /* CMD Time Out */
1196 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
1221 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
1284 #define SD4E 0x4 /* SDIO 4-Bit Enable */
1308 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */
1334 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
1348 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
1369 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
1390 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
1474 #define TIMEN10 0x4 /* Timer 10 Enable */
1483 #define TIMDIS10 0x4 /* Timer 10 Disable */
1492 #define TIMIL10 0x4 /* Timer 10 Interrupt */
1519 #define RESUME_MODE 0x4 /* DMA Mode */
1538 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
1555 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
1574 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
1591 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1610 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1629 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1656 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1689 #define HOST_MODE 0x4 /* indicates USBDRC is a host */
1708 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1723 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1738 #define STALL_SENT 0x4 /* STALL handshake sent */
1752 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1787 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1809 #define ERROR_TH 0x4 /* error condition host mode */
1826 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1850 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1891 #define DMA2_INT 0x4 /* DMA2 pending interrupt */
1910 #define MODE 0x4 /* DMA Bus error */