Lines Matching refs:bfin_write32
65 bfin_write32(SIC_IWR, IWR_ENABLE(0));
73 bfin_write32(SIC_IWR, iwr);
82 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
84 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
86 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
88 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
90 #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
92 #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
94 #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
100 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
102 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
106 #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
114 #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
172 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
174 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
184 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
186 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
199 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
201 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
211 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
213 #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
226 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
228 #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
238 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
240 #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
253 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
255 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
265 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
267 #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
280 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
282 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
292 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
294 #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
307 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
309 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
319 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
321 #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
334 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
336 #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
346 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
348 #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
361 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
363 #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
373 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
375 #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
388 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
390 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
400 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
402 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
415 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
417 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
427 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
429 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
442 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
444 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
454 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
456 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
469 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
471 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
481 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
483 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
497 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
499 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
503 #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
558 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
560 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
562 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
567 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
569 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
571 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
576 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
578 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
580 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
599 #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
601 #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
603 #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
605 #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
627 #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
629 #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
631 #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
633 #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
635 #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
637 #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
639 #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
641 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
653 #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
655 #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
657 #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
659 #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
681 #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
683 #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
685 #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
687 #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
689 #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
691 #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
693 #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
695 #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)