Lines Matching refs:x4
674 #define RESUME_MODE 0x4 /* DMA Mode */
693 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
710 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
729 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
746 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
765 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
784 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
811 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
844 #define HOST_MODE 0x4 /* indicates USBDRC is a host */
863 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
878 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
893 #define STALL_SENT 0x4 /* STALL handshake sent */
907 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
942 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
964 #define ERROR_TH 0x4 /* error condition host mode */
981 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1005 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1046 #define DMA2_INT 0x4 /* DMA2 pending interrupt */
1065 #define MODE 0x4 /* DMA Bus error */