Lines Matching refs:S3C24XX_GPIOREG2
33 #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
62 * S3C24XX_GPIOREG2 is for the second set of registers in the
66 #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
983 #define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)
1048 #define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
1049 #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
1050 #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
1065 #define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
1066 #define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
1067 #define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
1068 #define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
1094 #define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
1095 #define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
1096 #define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
1097 #define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
1098 #define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)