Lines Matching refs:AT91_PMC
19 #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
20 #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
22 #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
36 #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
37 #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
38 #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
40 #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
45 #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
49 #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
50 #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
57 #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
77 #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
79 #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
80 #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
81 #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
90 #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */