Lines Matching refs:TGA_WRITE_REG
279 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
285 TGA_WRITE_REG(par, deep_presets[tga_type] |
293 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
294 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
295 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
301 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
302 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
305 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
306 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
322 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
325 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
327 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
329 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
331 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
347 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
350 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
351 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
352 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
353 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
376 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
382 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
383 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
384 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
390 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
391 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
392 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
393 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
399 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
403 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
406 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
409 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
410 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
411 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
417 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
440 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
452 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
453 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
456 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
459 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
460 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
463 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
464 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
467 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
468 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
471 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
472 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
473 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
474 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
475 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
476 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
503 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
505 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
507 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
508 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
537 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
538 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
539 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
540 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
543 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
544 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
545 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
546 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
553 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
554 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
555 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
556 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
585 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
586 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
589 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
593 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
598 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
599 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
604 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
605 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
610 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
611 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
612 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);