Lines Matching defs:aty_ld_le32
516 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
533 return aty_ld_le32(CLOCK_CNTL_DATA);
584 val = aty_ld_le32(BIOS_0_SCRATCH);
587 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
590 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
608 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
625 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
649 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
655 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
666 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
671 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
673 aty_ld_le32(GEN_RESET_CNTL);
675 aty_ld_le32(GEN_RESET_CNTL);
787 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
791 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
958 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
1246 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1247 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1249 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1260 reg = aty_ld_le32(LVDS_GEN_CNTL);
1271 reg = aty_ld_le32(LVDS_GEN_CNTL);
1288 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1475 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1613 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1720 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1736 aty_ld_le32(LVDS_GEN_CNTL);
1749 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1757 aty_ld_le32(LVDS_GEN_CNTL);
1763 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1863 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1957 dac = aty_ld_le32(DAC_CNTL);
1965 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2045 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
2305 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &