Lines Matching refs:shadowMCR
118 __u8 shadowMCR; /* last MCR value received */
860 edge_port->shadowMCR = MCR_MASTER_IE; /* Must always set this bit to enable ints! */
1399 edge_port->shadowMCR &= ~MCR_RTS;
1400 status = send_cmd_write_uart_register(edge_port, MCR, edge_port->shadowMCR);
1448 edge_port->shadowMCR |= MCR_RTS;
1449 status = send_cmd_write_uart_register(edge_port, MCR, edge_port->shadowMCR);
1560 mcr = edge_port->shadowMCR;
1575 edge_port->shadowMCR = mcr;
1577 send_cmd_write_uart_register(edge_port, MCR, edge_port->shadowMCR);
1592 mcr = edge_port->shadowMCR;
2600 edge_port->shadowMCR = MCR_MASTER_IE;
2602 edge_port->shadowMCR |= (MCR_DTR | MCR_RTS);
2604 status = send_cmd_write_uart_register(edge_port, MCR, edge_port->shadowMCR);