Lines Matching defs:ucon
188 unsigned int ucon, ufcon;
200 ucon = rd_regl(port, S3C2410_UCON);
201 ucon |= S3C2410_UCON_RXIRQMODE;
202 wr_regl(port, S3C2410_UCON, ucon);
211 unsigned int ucon;
215 ucon = rd_regl(port, S3C2410_UCON);
216 ucon &= ~S3C2410_UCON_RXIRQMODE;
217 wr_regl(port, S3C2410_UCON, ucon);
450 unsigned int ucon;
454 ucon = rd_regl(port, S3C2410_UCON);
457 ucon |= S3C2410_UCON_SBREAK;
459 ucon &= ~S3C2410_UCON_SBREAK;
461 wr_regl(port, S3C2410_UCON, ucon);
805 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1168 wr_regl(port, S3C2410_UCON, cfg->ucon);
1243 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1246 ucon |= S3C2410_UCON_UCLK;
1248 ucon &= ~S3C2410_UCON_UCLK;
1250 wr_regl(port, S3C2410_UCON, ucon);
1257 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1260 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1271 wr_regl(port, S3C2410_UCON, cfg->ucon);
1346 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1350 ucon &= ~S3C2440_UCON_CLKMASK;
1353 ucon |= S3C2440_UCON_UCLK;
1355 ucon |= S3C2440_UCON_PCLK;
1357 ucon |= S3C2440_UCON_FCLK;
1363 wr_regl(port, S3C2410_UCON, ucon);
1371 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1374 switch (ucon & S3C2440_UCON_CLKMASK) {
1424 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1431 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1433 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1509 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1511 ucon &= ~S3C2412_UCON_CLKMASK;
1514 ucon |= S3C2440_UCON_UCLK;
1516 ucon |= S3C2440_UCON_PCLK;
1518 ucon |= S3C2412_UCON_USYSCLK;
1524 wr_regl(port, S3C2410_UCON, ucon);
1532 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1534 switch (ucon & S3C2412_UCON_CLKMASK) {
1558 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1565 ucon &= S3C2412_UCON_CLKMASK;
1567 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1721 unsigned int ucon;
1726 ucon = rd_regl(port, S3C2410_UCON);
1730 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1731 port, ulcon, ucon, ubrdiv);
1733 if ((ucon & 0xf) != 0) {