Lines Matching refs:uap
79 struct uart_amba_port *uap = (struct uart_amba_port *)port;
81 uap->im &= ~UART011_TXIM;
82 writew(uap->im, uap->port.membase + UART011_IMSC);
87 struct uart_amba_port *uap = (struct uart_amba_port *)port;
89 uap->im |= UART011_TXIM;
90 writew(uap->im, uap->port.membase + UART011_IMSC);
95 struct uart_amba_port *uap = (struct uart_amba_port *)port;
97 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
99 writew(uap->im, uap->port.membase + UART011_IMSC);
104 struct uart_amba_port *uap = (struct uart_amba_port *)port;
106 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
107 writew(uap->im, uap->port.membase + UART011_IMSC);
110 static void pl011_rx_chars(struct uart_amba_port *uap)
112 struct tty_struct *tty = uap->port.info->tty;
115 status = readw(uap->port.membase + UART01x_FR);
117 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
119 uap->port.icount.rx++;
128 uap->port.icount.brk++;
129 if (uart_handle_break(&uap->port))
132 uap->port.icount.parity++;
134 uap->port.icount.frame++;
136 uap->port.icount.overrun++;
138 ch &= uap->port.read_status_mask;
148 if (uart_handle_sysrq_char(&uap->port, ch & 255))
151 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
154 status = readw(uap->port.membase + UART01x_FR);
156 spin_unlock(&uap->port.lock);
158 spin_lock(&uap->port.lock);
161 static void pl011_tx_chars(struct uart_amba_port *uap)
163 struct circ_buf *xmit = &uap->port.info->xmit;
166 if (uap->port.x_char) {
167 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
168 uap->port.icount.tx++;
169 uap->port.x_char = 0;
172 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
173 pl011_stop_tx(&uap->port);
177 count = uap->port.fifosize >> 1;
179 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
181 uap->port.icount.tx++;
187 uart_write_wakeup(&uap->port);
190 pl011_stop_tx(&uap->port);
193 static void pl011_modem_status(struct uart_amba_port *uap)
197 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
199 delta = status ^ uap->old_status;
200 uap->old_status = status;
206 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
209 uap->port.icount.dsr++;
212 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
214 wake_up_interruptible(&uap->port.info->delta_msr_wait);
219 struct uart_amba_port *uap = dev_id;
223 spin_lock(&uap->port.lock);
225 status = readw(uap->port.membase + UART011_MIS);
230 uap->port.membase + UART011_ICR);
233 pl011_rx_chars(uap);
236 pl011_modem_status(uap);
238 pl011_tx_chars(uap);
243 status = readw(uap->port.membase + UART011_MIS);
248 spin_unlock(&uap->port.lock);
255 struct uart_amba_port *uap = (struct uart_amba_port *)port;
256 unsigned int status = readw(uap->port.membase + UART01x_FR);
262 struct uart_amba_port *uap = (struct uart_amba_port *)port;
264 unsigned int status = readw(uap->port.membase + UART01x_FR);
280 struct uart_amba_port *uap = (struct uart_amba_port *)port;
283 cr = readw(uap->port.membase + UART011_CR);
298 writew(cr, uap->port.membase + UART011_CR);
303 struct uart_amba_port *uap = (struct uart_amba_port *)port;
307 spin_lock_irqsave(&uap->port.lock, flags);
308 lcr_h = readw(uap->port.membase + UART011_LCRH);
313 writew(lcr_h, uap->port.membase + UART011_LCRH);
314 spin_unlock_irqrestore(&uap->port.lock, flags);
319 struct uart_amba_port *uap = (struct uart_amba_port *)port;
326 retval = clk_enable(uap->clk);
330 uap->port.uartclk = clk_get_rate(uap->clk);
335 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
340 uap->port.membase + UART011_IFLS);
346 writew(cr, uap->port.membase + UART011_CR);
347 writew(0, uap->port.membase + UART011_FBRD);
348 writew(1, uap->port.membase + UART011_IBRD);
349 writew(0, uap->port.membase + UART011_LCRH);
350 writew(0, uap->port.membase + UART01x_DR);
351 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
355 writew(cr, uap->port.membase + UART011_CR);
360 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
365 spin_lock_irq(&uap->port.lock);
366 uap->im = UART011_RXIM | UART011_RTIM;
367 writew(uap->im, uap->port.membase + UART011_IMSC);
368 spin_unlock_irq(&uap->port.lock);
373 clk_disable(uap->clk);
380 struct uart_amba_port *uap = (struct uart_amba_port *)port;
386 spin_lock_irq(&uap->port.lock);
387 uap->im = 0;
388 writew(uap->im, uap->port.membase + UART011_IMSC);
389 writew(0xffff, uap->port.membase + UART011_ICR);
390 spin_unlock_irq(&uap->port.lock);
395 free_irq(uap->port.irq, uap);
400 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
405 val = readw(uap->port.membase + UART011_LCRH);
407 writew(val, uap->port.membase + UART011_LCRH);
412 clk_disable(uap->clk);
583 struct uart_amba_port *uap = (struct uart_amba_port *)port;
585 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
587 writew(ch, uap->port.membase + UART01x_DR);
593 struct uart_amba_port *uap = amba_ports[co->index];
596 clk_enable(uap->clk);
601 old_cr = readw(uap->port.membase + UART011_CR);
604 writew(new_cr, uap->port.membase + UART011_CR);
606 uart_console_write(&uap->port, s, count, pl011_console_putchar);
613 status = readw(uap->port.membase + UART01x_FR);
615 writew(old_cr, uap->port.membase + UART011_CR);
617 clk_disable(uap->clk);
621 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
624 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
627 lcr_h = readw(uap->port.membase + UART011_LCRH);
642 ibrd = readw(uap->port.membase + UART011_IBRD);
643 fbrd = readw(uap->port.membase + UART011_FBRD);
645 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
651 struct uart_amba_port *uap;
664 uap = amba_ports[co->index];
665 if (!uap)
668 uap->port.uartclk = clk_get_rate(uap->clk);
673 pl011_console_get_options(uap, &baud, &parity, &bits);
675 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
706 struct uart_amba_port *uap;
719 uap = kmalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
720 if (uap == NULL) {
731 memset(uap, 0, sizeof(struct uart_amba_port));
732 uap->clk = clk_get(&dev->dev, "UARTCLK");
733 if (IS_ERR(uap->clk)) {
734 ret = PTR_ERR(uap->clk);
738 uap->port.dev = &dev->dev;
739 uap->port.mapbase = dev->res.start;
740 uap->port.membase = base;
741 uap->port.iotype = UPIO_MEM;
742 uap->port.irq = dev->irq[0];
743 uap->port.fifosize = 16;
744 uap->port.ops = &amba_pl011_pops;
745 uap->port.flags = UPF_BOOT_AUTOCONF;
746 uap->port.line = i;
748 amba_ports[i] = uap;
750 amba_set_drvdata(dev, uap);
751 ret = uart_add_one_port(&amba_reg, &uap->port);
755 clk_put(uap->clk);
759 kfree(uap);
767 struct uart_amba_port *uap = amba_get_drvdata(dev);
772 uart_remove_one_port(&amba_reg, &uap->port);
775 if (amba_ports[i] == uap)
778 iounmap(uap->port.membase);
779 clk_put(uap->clk);
780 kfree(uap);