Lines Matching defs:ha
295 static void ips_free_flash_copperhead(ips_ha_t * ha);
347 static int ips_abort_init(ips_ha_t * ha, int index);
353 static int ips_poll_for_flush_complete(ips_ha_t * ha);
354 static void ips_flush_and_reset(ips_ha_t *ha);
612 ips_setup_funclist(ips_ha_t * ha)
618 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
620 ha->func.isintr = ips_isintr_morpheus;
621 ha->func.isinit = ips_isinit_morpheus;
622 ha->func.issue = ips_issue_i2o_memio;
623 ha->func.init = ips_init_morpheus;
624 ha->func.statupd = ips_statupd_morpheus;
625 ha->func.reset = ips_reset_morpheus;
626 ha->func.intr = ips_intr_morpheus;
627 ha->func.enableint = ips_enable_int_morpheus;
628 } else if (IPS_USE_MEMIO(ha)) {
630 ha->func.isintr = ips_isintr_copperhead_memio;
631 ha->func.isinit = ips_isinit_copperhead_memio;
632 ha->func.init = ips_init_copperhead_memio;
633 ha->func.statupd = ips_statupd_copperhead_memio;
634 ha->func.statinit = ips_statinit_memio;
635 ha->func.reset = ips_reset_copperhead_memio;
636 ha->func.intr = ips_intr_copperhead;
637 ha->func.erasebios = ips_erase_bios_memio;
638 ha->func.programbios = ips_program_bios_memio;
639 ha->func.verifybios = ips_verify_bios_memio;
640 ha->func.enableint = ips_enable_int_copperhead_memio;
641 if (IPS_USE_I2O_DELIVER(ha))
642 ha->func.issue = ips_issue_i2o_memio;
644 ha->func.issue = ips_issue_copperhead_memio;
647 ha->func.isintr = ips_isintr_copperhead;
648 ha->func.isinit = ips_isinit_copperhead;
649 ha->func.init = ips_init_copperhead;
650 ha->func.statupd = ips_statupd_copperhead;
651 ha->func.statinit = ips_statinit;
652 ha->func.reset = ips_reset_copperhead;
653 ha->func.intr = ips_intr_copperhead;
654 ha->func.erasebios = ips_erase_bios;
655 ha->func.programbios = ips_program_bios;
656 ha->func.verifybios = ips_verify_bios;
657 ha->func.enableint = ips_enable_int_copperhead;
659 if (IPS_USE_I2O_DELIVER(ha))
660 ha->func.issue = ips_issue_i2o;
662 ha->func.issue = ips_issue_copperhead;
679 ips_ha_t *ha;
693 ha = IPS_HA(sh);
695 if (!ha)
699 scb = &ha->scbs[ha->max_cmds - 1];
701 ips_init_scb(ha, scb);
707 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
714 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
717 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
718 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
720 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
726 ips_free(ha);
729 if (ha->io_addr)
730 release_region(ha->io_addr, ha->io_len);
733 free_irq(ha->irq, ha);
756 ips_ha_t *ha;
764 ha = (ips_ha_t *) ips_ha[i];
766 if (!ha)
769 if (!ha->active)
773 scb = &ha->scbs[ha->max_cmds - 1];
775 ips_init_scb(ha, scb);
781 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
788 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
791 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
793 IPS_PRINTK(KERN_WARNING, ha->pcidev,
796 IPS_PRINTK(KERN_WARNING, ha->pcidev,
814 ips_ha_t *ha;
826 ha = (ips_ha_t *) SC->device->host->hostdata;
828 if (!ha)
831 if (!ha->active)
837 item = ha->copp_waitlist.head;
843 ips_removeq_copp(&ha->copp_waitlist, item);
847 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
874 ips_ha_t *ha;
890 ha = (ips_ha_t *) SC->device->host->hostdata;
892 if (!ha) {
893 DEBUG(1, "Reset called with NULL ha struct");
898 if (!ha->active)
902 item = ha->copp_waitlist.head;
908 ips_removeq_copp(&ha->copp_waitlist, item);
913 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
928 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
929 scb = &ha->scbs[ha->max_cmds - 1];
931 ips_init_scb(ha, scb);
937 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
945 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
947 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
956 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
962 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
963 ret = (*ha->func.reset) (ha);
968 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
973 ips_name, ha->host_num);
975 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
978 ips_freescb(ha, scb);
983 ips_name, ha->host_num);
985 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
990 ha->active = FALSE;
994 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
997 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
1002 ips_name, ha->host_num);
1004 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1007 ips_freescb(ha, scb);
1012 ips_name, ha->host_num);
1014 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
1019 ha->active = FALSE;
1024 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
1028 ha->last_ffdc = tv.tv_sec;
1029 ha->reset_count++;
1030 ips_ffdc_reset(ha, IPS_INTR_IORL);
1034 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1036 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1040 ips_freescb(ha, scb);
1044 for (i = 1; i < ha->nbus; i++)
1045 ha->dcdb_active[i - 1] = 0;
1048 ha->num_ioctl = 0;
1050 ips_next(ha, IPS_INTR_IORL);
1082 ips_ha_t *ha;
1087 ha = (ips_ha_t *) SC->device->host->hostdata;
1089 if (!ha)
1092 if (!ha->active)
1096 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1102 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1113 ha->host_num,
1119 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1136 if (ha->scb_activelist.count != 0) {
1141 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1161 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1163 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1166 ips_next(ha, IPS_INTR_IORL);
1184 ips_ha_t *ha = (ips_ha_t *) disk->device->host->hostdata;
1190 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1198 if (!ha)
1202 if (!ha->active)
1205 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1209 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1261 ips_ha_t *ha;
1265 ha = IPS_HA(host);
1266 min = ha->max_cmds / 4;
1279 (ha->max_cmds - 1) / count;
1305 ips_ha_t *ha;
1308 ha = IPS_HA(SDptr->host);
1310 min = ha->max_cmds / 2;
1311 if (ha->enq->ucLogDriveCount <= 2)
1312 min = ha->max_cmds - 1;
1334 ips_ha_t *ha;
1341 ha = (ips_ha_t *) dev_id;
1342 if (!ha)
1344 host = ips_sh[ha->host_num];
1347 (*ha->func.intr) (ha);
1353 if (!ha->active) {
1358 irqstatus = (*ha->func.intr) (ha);
1363 ips_next(ha, IPS_INTR_ON);
1379 ips_intr_copperhead(ips_ha_t * ha)
1388 if (!ha)
1391 if (!ha->active)
1394 intrstatus = (*ha->func.isintr) (ha);
1405 sp = &ha->sp;
1407 intrstatus = (*ha->func.isintr) (ha);
1412 cstatus.value = (*ha->func.statupd) (ha);
1419 ips_chkstatus(ha, &cstatus);
1426 (*scb->callback) (ha, scb);
1443 ips_intr_morpheus(ips_ha_t * ha)
1452 if (!ha)
1455 if (!ha->active)
1458 intrstatus = (*ha->func.isintr) (ha);
1469 sp = &ha->sp;
1471 intrstatus = (*ha->func.isintr) (ha);
1476 cstatus.value = (*ha->func.statupd) (ha);
1483 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1489 ips_chkstatus(ha, &cstatus);
1496 (*scb->callback) (ha, scb);
1515 ips_ha_t *ha;
1519 ha = IPS_HA(SH);
1521 if (!ha)
1530 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1532 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1554 ips_ha_t *ha = NULL;
1562 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1568 if (!ha)
1579 ret = ips_host_info(ha, buffer, offset, length);
1647 ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1652 if (ha->ioctl_data && length <= ha->ioctl_len)
1655 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1658 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1659 ha->ioctl_busaddr);
1661 ha->ioctl_data = (char *) bigger_buf;
1662 ha->ioctl_len = length;
1663 ha->ioctl_busaddr = dma_busaddr;
1680 ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1699 ips_name, ha->host_num);
1702 if (ips_alloc_passthru_buffer(ha, length)) {
1703 /* allocation failure! If ha->ioctl_data exists, use it to return
1705 if (ha->ioctl_data) {
1706 pt = (ips_passthru_t *) ha->ioctl_data;
1714 ha->ioctl_datasize = length;
1716 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1717 pt = (ips_passthru_t *) ha->ioctl_data;
1731 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1733 ips_scmd_buf_write(SC, ha->ioctl_data,
1746 ips_name, ha->host_num);
1751 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
1754 ret = ips_flash_copperhead(ha, pt, scb);
1755 ips_scmd_buf_write(SC, ha->ioctl_data,
1759 if (ips_usrcmd(ha, pt, scb))
1778 ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1784 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1785 if (ips_usrcmd(ha, pt, scb))
1798 return ips_flash_bios(ha, pt, scb);
1801 ha->flash_data = ips_FlashData;
1802 ha->flash_busaddr = ips_flashbusaddr;
1803 ha->flash_len = PAGE_SIZE << 7;
1804 ha->flash_datasize = 0;
1805 } else if (!ha->flash_data) {
1808 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1810 &ha->flash_busaddr);
1811 if (!ha->flash_data){
1815 ha->flash_datasize = 0;
1816 ha->flash_len = datasize;
1820 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1821 ha->flash_len) {
1822 ips_free_flash_copperhead(ha);
1823 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1828 if (!ha->flash_data)
1831 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1833 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1837 return ips_flash_bios(ha, pt, scb);
1839 return ips_flash_firmware(ha, pt, scb);
1850 ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1855 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1856 (!ha->func.verifybios))
1858 if ((*ha->func.erasebios) (ha)) {
1861 ips_name, ha->host_num);
1864 if ((*ha->func.programbios) (ha,
1865 ha->flash_data +
1867 ha->flash_datasize -
1871 ips_name, ha->host_num);
1874 if ((*ha->func.verifybios) (ha,
1875 ha->flash_data +
1877 ha->flash_datasize -
1881 ips_name, ha->host_num);
1884 ips_free_flash_copperhead(ha);
1888 if (!ha->func.erasebios)
1890 if ((*ha->func.erasebios) (ha)) {
1893 ips_name, ha->host_num);
1901 ips_free_flash_copperhead(ha);
1914 ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1920 if ((scb->data_len + e_len) > ha->max_xfer) {
1921 e_len = ha->max_xfer - scb->data_len;
1929 if (IPS_USE_ENH_SGLIST(ha)) {
1952 ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1961 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1965 ips_free_flash_copperhead(ha);
1986 scb->data_len = ha->flash_datasize;
1988 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1991 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2005 ips_free_flash_copperhead(ips_ha_t * ha)
2007 if (ha->flash_data == ips_FlashData)
2009 else if (ha->flash_data)
2010 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
2011 ha->flash_busaddr);
2012 ha->flash_data = NULL;
2025 ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
2032 if ((!scb) || (!pt) || (!ha))
2054 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
2064 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
2113 ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
2121 ips_name, ha->host_num);
2125 pt = (ips_passthru_t *) ha->ioctl_data;
2133 pt->AdapterType = ha->ad_type;
2135 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
2138 ips_free_flash_copperhead(ha);
2140 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2153 ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len)
2167 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2168 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2170 ips_adapter_name[ha->ad_type - 1]);
2175 if (ha->io_addr)
2178 ha->io_addr, ha->io_len);
2180 if (ha->mem_addr) {
2183 ha->mem_addr, ha->mem_len);
2186 ha->mem_ptr);
2189 copy_info(&info, "\tIRQ number : %d\n", ha->irq);
2194 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2195 if (ha->nvram->bios_low[3] == 0) {
2198 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2199 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2200 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2201 ha->nvram->bios_low[2]);
2206 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2207 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2208 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2209 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2214 if (ha->enq->CodeBlkVersion[7] == 0) {
2217 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2218 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2219 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2220 ha->enq->CodeBlkVersion[6]);
2224 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2225 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2226 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2227 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2230 if (ha->enq->BootBlkVersion[7] == 0) {
2233 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2234 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2235 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2236 ha->enq->BootBlkVersion[6]);
2240 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2241 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2242 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2243 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2253 ha->enq->ucMaxPhysicalDevices);
2255 ha->max_cmds);
2257 ha->scb_waitlist.count);
2259 ha->scb_activelist.count - ha->num_ioctl);
2261 ha->copp_waitlist.count);
2263 ha->num_ioctl);
2342 ips_identify_controller(ips_ha_t * ha)
2346 switch (ha->device_id) {
2348 if (ha->revision_id <= IPS_REVID_SERVERAID) {
2349 ha->ad_type = IPS_ADTYPE_SERVERAID;
2350 } else if (ha->revision_id == IPS_REVID_SERVERAID2) {
2351 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2352 } else if (ha->revision_id == IPS_REVID_NAVAJO) {
2353 ha->ad_type = IPS_ADTYPE_NAVAJO;
2354 } else if ((ha->revision_id == IPS_REVID_SERVERAID2)
2355 && (ha->slot_num == 0)) {
2356 ha->ad_type = IPS_ADTYPE_KIOWA;
2357 } else if ((ha->revision_id >= IPS_REVID_CLARINETP1) &&
2358 (ha->revision_id <= IPS_REVID_CLARINETP3)) {
2359 if (ha->enq->ucMaxPhysicalDevices == 15)
2360 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2362 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2363 } else if ((ha->revision_id >= IPS_REVID_TROMBONE32) &&
2364 (ha->revision_id <= IPS_REVID_TROMBONE64)) {
2365 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2370 switch (ha->subdevice_id) {
2372 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2376 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2380 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2384 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2388 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2392 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2399 switch (ha->subdevice_id) {
2401 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2404 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2407 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2410 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2427 ips_get_bios_version(ips_ha_t * ha, int intr)
2444 strncpy(ha->bios_version, " ?", 8);
2446 if (ha->device_id == IPS_DEVICEID_COPPERHEAD) {
2447 if (IPS_USE_MEMIO(ha)) {
2451 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2452 if (ha->revision_id == IPS_REVID_TROMBONE64)
2455 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2458 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2459 if (ha->revision_id == IPS_REVID_TROMBONE64)
2462 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2466 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2467 if (ha->revision_id == IPS_REVID_TROMBONE64)
2470 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2473 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2474 if (ha->revision_id == IPS_REVID_TROMBONE64)
2476 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2479 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2480 if (ha->revision_id == IPS_REVID_TROMBONE64)
2482 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2488 outl(0, ha->io_addr + IPS_REG_FLAP);
2489 if (ha->revision_id == IPS_REVID_TROMBONE64)
2492 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2495 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
2496 if (ha->revision_id == IPS_REVID_TROMBONE64)
2499 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2503 outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP);
2504 if (ha->revision_id == IPS_REVID_TROMBONE64)
2507 major = inb(ha->io_addr + IPS_REG_FLDP);
2510 outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP);
2511 if (ha->revision_id == IPS_REVID_TROMBONE64)
2514 minor = inb(ha->io_addr + IPS_REG_FLDP);
2517 outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP);
2518 if (ha->revision_id == IPS_REVID_TROMBONE64)
2521 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2527 buffer = ha->ioctl_data;
2531 scb = &ha->scbs[ha->max_cmds - 1];
2533 ips_init_scb(ha, scb);
2539 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2546 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2550 ips_send_wait(ha, scb, ips_cmd_timeout,
2568 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4];
2569 ha->bios_version[1] = '.';
2570 ha->bios_version[2] = hexDigits[major & 0x0F];
2571 ha->bios_version[3] = hexDigits[subminor];
2572 ha->bios_version[4] = '.';
2573 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4];
2574 ha->bios_version[6] = hexDigits[minor & 0x0F];
2575 ha->bios_version[7] = 0;
2590 ips_hainit(ips_ha_t * ha)
2597 if (!ha)
2600 if (ha->func.statinit)
2601 (*ha->func.statinit) (ha);
2603 if (ha->func.enableint)
2604 (*ha->func.enableint) (ha);
2607 ha->reset_count = 1;
2609 ha->last_ffdc = tv.tv_sec;
2610 ips_ffdc_reset(ha, IPS_INTR_IORL);
2612 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2613 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2619 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2620 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2627 ips_identify_controller(ha);
2629 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2630 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2637 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2638 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2645 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2646 ips_clear_adapter(ha, IPS_INTR_IORL);
2649 ha->ntargets = IPS_MAX_TARGETS + 1;
2650 ha->nlun = 1;
2651 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2653 switch (ha->conf->logical_drive[0].ucStripeSize) {
2655 ha->max_xfer = 0x10000;
2659 ha->max_xfer = 0x20000;
2663 ha->max_xfer = 0x40000;
2668 ha->max_xfer = 0x80000;
2673 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2675 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2678 switch (ha->conf->logical_drive[0].ucStripeSize) {
2680 ha->max_cmds = 32;
2684 ha->max_cmds = 16;
2688 ha->max_cmds = 8;
2693 ha->max_cmds = 4;
2699 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2700 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2701 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2702 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2703 ha->max_cmds = MaxLiteCmds;
2707 ha->ha_id[0] = IPS_ADAPTER_ID;
2708 for (i = 1; i < ha->nbus; i++) {
2709 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2710 ha->dcdb_active[i - 1] = 0;
2726 ips_next(ips_ha_t * ha, int intr)
2738 if (!ha)
2740 host = ips_sh[ha->host_num];
2748 if ((ha->subsys->param[3] & 0x300000)
2749 && (ha->scb_activelist.count == 0)) {
2754 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2755 ha->last_ffdc = tv.tv_sec;
2756 ips_ffdc_time(ha);
2767 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2768 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2770 item = ips_removeq_copp_head(&ha->copp_waitlist);
2771 ha->num_ioctl++;
2777 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2788 ips_freescb(ha, scb);
2796 ips_freescb(ha, scb);
2803 ha->num_ioctl--;
2807 ret = ips_send_cmd(ha, scb);
2810 ips_putq_scb_head(&ha->scb_activelist, scb);
2812 ha->num_ioctl--;
2820 ips_freescb(ha, scb);
2823 ips_freescb(ha, scb);
2835 p = ha->scb_waitlist.head;
2836 while ((p) && (scb = ips_getscb(ha))) {
2838 && (ha->
2841 ips_freescb(ha, scb);
2847 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2876 scb->sg_count = pci_map_sg(ha->pcidev, sg, SC->use_sg,
2881 (ha, sg_dma_address(&sg[i]), scb, i,
2889 pci_map_single(ha->pcidev,
2894 ips_fill_scb_sg_single(ha, scb->data_busaddr,
2925 ret = ips_send_cmd(ha, scb);
2929 ips_putq_scb_head(&ha->scb_activelist, scb);
2938 ha->dcdb_active[scb->bus - 1] &=
2941 ips_freescb(ha, scb);
2948 ha->dcdb_active[scb->bus - 1] &=
2951 ips_freescb(ha, scb);
3308 ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3312 ips_freescb(ha, scb);
3313 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3314 ha->waitflag = FALSE;
3330 ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3335 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3343 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3349 ips_done(ha, scb);
3362 ips_done(ips_ha_t * ha, ips_scb_t * scb)
3372 ips_cleanup_passthru(ha, scb);
3373 ha->num_ioctl--;
3396 ips_fill_scb_sg_single(ha,
3406 (ha,
3416 (void) ips_fill_scb_sg_single(ha,
3420 ha->max_xfer),
3425 ha->max_xfer));
3440 ret = ips_send_cmd(ha, scb);
3449 ips_freescb(ha, scb);
3457 ips_freescb(ha, scb);
3468 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3473 ips_freescb(ha, scb);
3486 ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3499 ips_name, ha->host_num,
3625 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3632 ha->waitflag = TRUE;
3633 ha->cmd_in_progress = scb->cdb[0];
3636 ret = ips_send_cmd(ha, scb);
3642 ret = ips_wait(ha, timeout, intr);
3733 ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3751 if ((ha->waitflag == TRUE) &&
3752 (ha->cmd_in_progress == scb->cdb[0])) {
3753 ha->waitflag = FALSE;
3818 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3822 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3831 ips_reqsen(ha, scb);
3850 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3856 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3898 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3904 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3945 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3948 scb->data_len = sizeof (*ha->enq);
3949 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3955 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3960 scb->data_busaddr = ha->logical_drive_info_dma_addr;
4004 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
4009 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
4010 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
4023 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
4030 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
4069 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
4107 return ((*ha->func.issue) (ha, scb));
4120 ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
4131 scb = &ha->scbs[pstatus->fields.command_id];
4136 sp = &ha->sp;
4141 ips_removeq_scb(&ha->scb_activelist, scb);
4149 ha->host_num,
4168 ips_name, ha->host_num,
4186 if (!ips_online(ha, scb)) {
4192 if (ips_online(ha, scb)) {
4193 ips_inquiry(ha, scb);
4200 ips_reqsen(ha, scb);
4212 if (!ips_online(ha, scb)
4213 || !ips_msense(ha, scb)) {
4219 if (ips_online(ha, scb))
4220 ips_rdcap(ha, scb);
4259 ips_name, ha->host_num,
4264 ips_map_status(ha, scb, sp);
4278 ips_online(ips_ha_t * ha, ips_scb_t * scb)
4286 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4290 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4292 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4294 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4296 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4313 ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4348 ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4359 (ha->logical_drive_info->
4378 ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4387 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4388 (ha->enq->ucMiscFlag & 0x8) == 0) {
4397 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4469 ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4498 ips_free(ips_ha_t * ha)
4503 if (ha) {
4504 if (ha->enq) {
4505 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4506 ha->enq, ha->enq_busaddr);
4507 ha->enq = NULL;
4510 kfree(ha->conf);
4511 ha->conf = NULL;
4513 if (ha->adapt) {
4514 pci_free_consistent(ha->pcidev,
4516 sizeof (IPS_IO_CMD), ha->adapt,
4517 ha->adapt->hw_status_start);
4518 ha->adapt = NULL;
4521 if (ha->logical_drive_info) {
4522 pci_free_consistent(ha->pcidev,
4524 ha->logical_drive_info,
4525 ha->logical_drive_info_dma_addr);
4526 ha->logical_drive_info = NULL;
4529 kfree(ha->nvram);
4530 ha->nvram = NULL;
4532 kfree(ha->subsys);
4533 ha->subsys = NULL;
4535 if (ha->ioctl_data) {
4536 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4537 ha->ioctl_data, ha->ioctl_busaddr);
4538 ha->ioctl_data = NULL;
4539 ha->ioctl_datasize = 0;
4540 ha->ioctl_len = 0;
4542 ips_deallocatescbs(ha, ha->max_cmds);
4545 if (ha->mem_ptr) {
4546 iounmap(ha->ioremap_ptr);
4547 ha->ioremap_ptr = NULL;
4548 ha->mem_ptr = NULL;
4551 if (ha->mem_addr)
4552 release_mem_region(ha->mem_addr, ha->mem_len);
4553 ha->mem_addr = 0;
4568 ips_deallocatescbs(ips_ha_t * ha, int cmds)
4570 if (ha->scbs) {
4571 pci_free_consistent(ha->pcidev,
4572 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4573 ha->scbs->sg_list.list,
4574 ha->scbs->sg_busaddr);
4575 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4576 ha->scbs, ha->scbs->scb_busaddr);
4577 ha->scbs = NULL;
4592 ips_allocatescbs(ips_ha_t * ha)
4602 ha->scbs =
4603 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4605 if (ha->scbs == NULL)
4608 pci_alloc_consistent(ha->pcidev,
4609 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4610 ha->max_cmds, &sg_dma);
4612 pci_free_consistent(ha->pcidev,
4613 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4618 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4620 for (i = 0; i < ha->max_cmds; i++) {
4621 scb_p = &ha->scbs[i];
4624 if (IPS_USE_ENH_SGLIST(ha)) {
4628 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4633 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4637 if (i < ha->max_cmds - 1) {
4638 scb_p->q_next = ha->scb_freelist;
4639 ha->scb_freelist = scb_p;
4657 ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4671 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4674 ha->dummy->op_code = 0xFF;
4675 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4677 ha->dummy->command_id = IPS_MAX_CMDS;
4686 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4702 ips_getscb(ips_ha_t * ha)
4708 if ((scb = ha->scb_freelist) == NULL) {
4713 ha->scb_freelist = scb->q_next;
4717 ips_init_scb(ha, scb);
4734 ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4739 pci_unmap_sg(ha->pcidev, scb->scsi_cmd->request_buffer,
4742 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4746 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4747 scb->q_next = ha->scb_freelist;
4748 ha->scb_freelist = scb;
4762 ips_isinit_copperhead(ips_ha_t * ha)
4769 isr = inb(ha->io_addr + IPS_REG_HISR);
4770 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4788 ips_isinit_copperhead_memio(ips_ha_t * ha)
4795 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4796 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4814 ips_isinit_morpheus(ips_ha_t * ha)
4821 if (ips_isintr_morpheus(ha))
4822 ips_flush_and_reset(ha);
4824 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4825 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4846 ips_flush_and_reset(ips_ha_t *ha)
4855 scb = pci_alloc_consistent(ha->pcidev, sizeof(ips_scb_t), &command_dma);
4858 ips_init_scb(ha, scb);
4872 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */
4879 done = ips_poll_for_flush_complete(ha);
4888 (*ha->func.reset) (ha);
4890 pci_free_consistent(ha->pcidev, sizeof(ips_scb_t), scb, command_dma);
4905 ips_poll_for_flush_complete(ips_ha_t * ha)
4910 cstatus.value = (*ha->func.statupd) (ha);
4932 ips_enable_int_copperhead(ips_ha_t * ha)
4936 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4937 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4949 ips_enable_int_copperhead_memio(ips_ha_t * ha)
4953 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4954 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4966 ips_enable_int_morpheus(ips_ha_t * ha)
4972 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4974 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4975 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4988 ips_init_copperhead(ips_ha_t * ha)
5000 Isr = inb(ha->io_addr + IPS_REG_HISR);
5012 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
5013 outb(Isr, ha->io_addr + IPS_REG_HISR);
5017 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5026 Isr = inb(ha->io_addr + IPS_REG_HISR);
5038 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
5039 outb(Isr, ha->io_addr + IPS_REG_HISR);
5043 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
5057 outl(cpu_to_le32(0x1010), ha->io_addr + IPS_REG_CCCR);
5060 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
5062 if (ha->revision_id == IPS_REVID_TROMBONE64)
5064 outl(0, ha->io_addr + IPS_REG_NDAE);
5067 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
5082 ips_init_copperhead_memio(ips_ha_t * ha)
5094 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5106 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
5107 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5111 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5120 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5132 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
5133 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5137 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
5151 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
5154 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
5156 if (ha->revision_id == IPS_REVID_TROMBONE64)
5158 writel(0, ha->mem_ptr + IPS_REG_NDAE);
5161 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
5177 ips_init_morpheus(ips_ha_t * ha)
5189 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5200 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5206 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5209 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5214 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5217 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5225 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5234 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5237 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5245 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5256 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5262 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
5266 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5269 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
5271 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
5278 ha->requires_esl = 1;
5294 ips_reset_copperhead(ips_ha_t * ha)
5301 ips_name, ha->host_num, ha->io_addr, ha->irq);
5308 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5313 outb(0, ha->io_addr + IPS_REG_SCPR);
5318 if ((*ha->func.init) (ha))
5339 ips_reset_copperhead_memio(ips_ha_t * ha)
5346 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5353 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5358 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5363 if ((*ha->func.init) (ha))
5384 ips_reset_morpheus(ips_ha_t * ha)
5392 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5399 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5405 pci_read_config_byte(ha->pcidev, 4, &junk);
5407 if ((*ha->func.init) (ha))
5428 ips_statinit(ips_ha_t * ha)
5434 ha->adapt->p_status_start = ha->adapt->status;
5435 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5436 ha->adapt->p_status_tail = ha->adapt->status;
5438 phys_status_start = ha->adapt->hw_status_start;
5439 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQSR);
5441 ha->io_addr + IPS_REG_SQER);
5443 ha->io_addr + IPS_REG_SQHR);
5444 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQTR);
5446 ha->adapt->hw_status_tail = phys_status_start;
5459 ips_statinit_memio(ips_ha_t * ha)
5465 ha->adapt->p_status_start = ha->adapt->status;
5466 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5467 ha->adapt->p_status_tail = ha->adapt->status;
5469 phys_status_start = ha->adapt->hw_status_start;
5470 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5472 ha->mem_ptr + IPS_REG_SQER);
5473 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5474 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5476 ha->adapt->hw_status_tail = phys_status_start;
5489 ips_statupd_copperhead(ips_ha_t * ha)
5493 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5494 ha->adapt->p_status_tail++;
5495 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5497 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5498 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5501 outl(cpu_to_le32(ha->adapt->hw_status_tail),
5502 ha->io_addr + IPS_REG_SQTR);
5504 return (ha->adapt->p_status_tail->value);
5517 ips_statupd_copperhead_memio(ips_ha_t * ha)
5521 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5522 ha->adapt->p_status_tail++;
5523 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5525 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5526 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5529 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5531 return (ha->adapt->p_status_tail->value);
5544 ips_statupd_morpheus(ips_ha_t * ha)
5550 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5565 ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5575 ha->host_num,
5581 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5587 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5594 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5596 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5603 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_CCSAR);
5604 outw(cpu_to_le32(IPS_BIT_START_CMD), ha->io_addr + IPS_REG_CCCR);
5619 ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5629 ha->host_num,
5635 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5640 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5647 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5649 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5656 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5657 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5672 ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5680 ha->host_num,
5686 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5689 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_I2O_INMSGQ);
5704 ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5712 ha->host_num,
5718 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5721 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5736 ips_isintr_copperhead(ips_ha_t * ha)
5742 Isr = inb(ha->io_addr + IPS_REG_HISR);
5753 outb(Isr, ha->io_addr + IPS_REG_HISR);
5769 ips_isintr_copperhead_memio(ips_ha_t * ha)
5775 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5786 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5802 ips_isintr_morpheus(ips_ha_t * ha)
5808 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5826 ips_wait(ips_ha_t * ha, int time, int intr)
5840 if (ha->waitflag == FALSE) {
5846 if (ha->waitflag == FALSE) {
5863 (*ha->func.intr) (ha);
5884 ips_write_driver_status(ips_ha_t * ha, int intr)
5888 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5889 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5897 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5900 ips_name, ha->host_num, ha->nvram->signature);
5901 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5906 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5907 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5908 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5909 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5910 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5911 ha->nvram->bios_low[3]);
5913 ips_get_bios_version(ha, intr);
5916 ha->nvram->operating_system = IPS_OS_LINUX;
5917 ha->nvram->adapter_type = ha->ad_type;
5918 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5919 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5920 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5921 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5923 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */
5926 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5927 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5934 ha->slot_num = ha->nvram->adapter_slot;
5949 ips_read_adapter_status(ips_ha_t * ha, int intr)
5956 scb = &ha->scbs[ha->max_cmds - 1];
5958 ips_init_scb(ha, scb);
5964 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5969 scb->data_len = sizeof (*ha->enq);
5970 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5974 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5992 ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5999 scb = &ha->scbs[ha->max_cmds - 1];
6001 ips_init_scb(ha, scb);
6007 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
6012 scb->data_len = sizeof (*ha->subsys);
6013 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
6017 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6022 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
6036 ips_read_config(ips_ha_t * ha, int intr)
6046 ha->conf->init_id[i] = 7;
6048 scb = &ha->scbs[ha->max_cmds - 1];
6050 ips_init_scb(ha, scb);
6056 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
6057 scb->data_len = sizeof (*ha->conf);
6058 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
6062 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6066 memset(ha->conf, 0, sizeof (IPS_CONF));
6070 ha->conf->init_id[i] = 7;
6080 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
6094 ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
6101 scb = &ha->scbs[ha->max_cmds - 1];
6103 ips_init_scb(ha, scb);
6109 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
6114 scb->data_len = sizeof (*ha->nvram);
6115 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
6117 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
6121 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6125 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
6130 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
6144 ips_clear_adapter(ips_ha_t * ha, int intr)
6151 scb = &ha->scbs[ha->max_cmds - 1];
6153 ips_init_scb(ha, scb);
6159 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
6168 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
6174 ips_init_scb(ha, scb);
6180 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
6189 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6207 ips_ffdc_reset(ips_ha_t * ha, int intr)
6213 scb = &ha->scbs[ha->max_cmds - 1];
6215 ips_init_scb(ha, scb);
6220 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6221 scb->cmd.ffdc.reset_count = ha->reset_count;
6225 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6228 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6241 ips_ffdc_time(ips_ha_t * ha)
6247 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
6249 scb = &ha->scbs[ha->max_cmds - 1];
6251 ips_init_scb(ha, scb);
6256 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6261 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6264 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
6276 ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
6344 ips_erase_bios(ips_ha_t * ha)
6354 outl(0, ha->io_addr + IPS_REG_FLAP);
6355 if (ha->revision_id == IPS_REVID_TROMBONE64)
6358 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6359 if (ha->revision_id == IPS_REVID_TROMBONE64)
6363 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6364 if (ha->revision_id == IPS_REVID_TROMBONE64)
6368 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6369 if (ha->revision_id == IPS_REVID_TROMBONE64)
6373 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6374 if (ha->revision_id == IPS_REVID_TROMBONE64)
6380 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6381 outl(0, ha->io_addr + IPS_REG_FLAP);
6385 status = inb(ha->io_addr + IPS_REG_FLDP);
6399 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6400 if (ha->revision_id == IPS_REVID_TROMBONE64)
6406 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6407 outl(0, ha->io_addr + IPS_REG_FLAP);
6411 status = inb(ha->io_addr + IPS_REG_FLDP);
6435 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6436 if (ha->revision_id == IPS_REVID_TROMBONE64)
6440 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6441 if (ha->revision_id == IPS_REVID_TROMBONE64)
6456 ips_erase_bios_memio(ips_ha_t * ha)
6466 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6467 if (ha->revision_id == IPS_REVID_TROMBONE64)
6470 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6471 if (ha->revision_id == IPS_REVID_TROMBONE64)
6475 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6476 if (ha->revision_id == IPS_REVID_TROMBONE64)
6480 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6481 if (ha->revision_id == IPS_REVID_TROMBONE64)
6485 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6486 if (ha->revision_id == IPS_REVID_TROMBONE64)
6492 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6493 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6497 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6511 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6512 if (ha->revision_id == IPS_REVID_TROMBONE64)
6518 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6519 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6523 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6547 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6548 if (ha->revision_id == IPS_REVID_TROMBONE64)
6552 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6553 if (ha->revision_id == IPS_REVID_TROMBONE64)
6568 ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6581 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6582 if (ha->revision_id == IPS_REVID_TROMBONE64)
6585 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6586 if (ha->revision_id == IPS_REVID_TROMBONE64)
6589 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6590 if (ha->revision_id == IPS_REVID_TROMBONE64)
6596 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6597 outl(0, ha->io_addr + IPS_REG_FLAP);
6601 status = inb(ha->io_addr + IPS_REG_FLDP);
6612 outl(0, ha->io_addr + IPS_REG_FLAP);
6613 if (ha->revision_id == IPS_REVID_TROMBONE64)
6616 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6617 if (ha->revision_id == IPS_REVID_TROMBONE64)
6626 outl(0, ha->io_addr + IPS_REG_FLAP);
6627 if (ha->revision_id == IPS_REVID_TROMBONE64)
6630 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6631 if (ha->revision_id == IPS_REVID_TROMBONE64)
6639 outl(0, ha->io_addr + IPS_REG_FLAP);
6640 if (ha->revision_id == IPS_REVID_TROMBONE64)
6643 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6644 if (ha->revision_id == IPS_REVID_TROMBONE64)
6659 ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6672 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6673 if (ha->revision_id == IPS_REVID_TROMBONE64)
6676 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6677 if (ha->revision_id == IPS_REVID_TROMBONE64)
6680 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6681 if (ha->revision_id == IPS_REVID_TROMBONE64)
6687 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6688 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6692 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6703 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6704 if (ha->revision_id == IPS_REVID_TROMBONE64)
6707 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6708 if (ha->revision_id == IPS_REVID_TROMBONE64)
6717 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6718 if (ha->revision_id == IPS_REVID_TROMBONE64)
6721 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6722 if (ha->revision_id == IPS_REVID_TROMBONE64)
6730 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6731 if (ha->revision_id == IPS_REVID_TROMBONE64)
6734 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6735 if (ha->revision_id == IPS_REVID_TROMBONE64)
6750 ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6759 outl(0, ha->io_addr + IPS_REG_FLAP);
6760 if (ha->revision_id == IPS_REVID_TROMBONE64)
6763 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6766 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
6767 if (ha->revision_id == IPS_REVID_TROMBONE64)
6769 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6775 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6776 if (ha->revision_id == IPS_REVID_TROMBONE64)
6779 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6799 ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6808 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6809 if (ha->revision_id == IPS_REVID_TROMBONE64)
6812 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6815 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6816 if (ha->revision_id == IPS_REVID_TROMBONE64)
6818 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6824 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6825 if (ha->revision_id == IPS_REVID_TROMBONE64)
6829 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6848 ips_abort_init(ips_ha_t * ha, int index)
6850 ha->active = 0;
6851 ips_free(ha);
6987 ips_ha_t *ha, *oldha = ips_ha[index];
6994 ha = IPS_HA(sh);
6995 memcpy(ha, oldha, sizeof (ips_ha_t));
6997 /* Install the interrupt handler with the new ha */
6998 if (request_irq(ha->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6999 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7007 ips_ha[index] = ha;
7008 IPS_SCSI_SET_DEVICE(sh, ha);
7011 sh->io_port = ha->io_addr;
7012 sh->n_io_port = ha->io_addr ? 255 : 0;
7013 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
7014 sh->irq = ha->irq;
7025 sh->max_id = ha->ntargets;
7026 sh->max_lun = ha->nlun;
7027 sh->max_channel = ha->nbus - 1;
7028 sh->can_queue = ha->max_cmds - 1;
7045 ips_ha_t *ha;
7048 ha = ips_ha[i];
7049 if (ha) {
7050 if ((pci_dev->bus->number == ha->pcidev->bus->number) &&
7051 (pci_dev->devfn == ha->pcidev->devfn)) {
7147 ips_ha_t *ha;
7240 ha = kmalloc(sizeof (ips_ha_t), GFP_KERNEL);
7241 if (ha == NULL) {
7243 "Unable to allocate temporary ha struct\n");
7247 memset(ha, 0, sizeof (ips_ha_t));
7250 ips_ha[index] = ha;
7251 ha->active = 1;
7254 ha->irq = irq;
7255 ha->io_addr = io_addr;
7256 ha->io_len = io_len;
7257 ha->mem_addr = mem_addr;
7258 ha->mem_len = mem_len;
7259 ha->mem_ptr = mem_ptr;
7260 ha->ioremap_ptr = ioremap_ptr;
7261 ha->host_num = (uint32_t) index;
7262 ha->revision_id = revision_id;
7263 ha->slot_num = PCI_SLOT(pci_dev->devfn);
7264 ha->device_id = pci_dev->device;
7265 ha->subdevice_id = subdevice_id;
7266 ha->pcidev = pci_dev;
7274 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
7275 !pci_set_dma_mask(ha->pcidev, DMA_64BIT_MASK)) {
7276 (ha)->flags |= IPS_HA_ENH_SG;
7278 if (pci_set_dma_mask(ha->pcidev, DMA_32BIT_MASK) != 0) {
7280 return ips_abort_init(ha, index);
7288 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
7289 &ha->enq_busaddr);
7290 if (!ha->enq) {
7293 return ips_abort_init(ha, index);
7296 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7298 if (!ha->adapt) {
7301 return ips_abort_init(ha, index);
7303 ha->adapt->hw_status_start = dma_address;
7304 ha->dummy = (void *) (ha->adapt + 1);
7308 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7309 if (!ha->logical_drive_info) {
7312 return ips_abort_init(ha, index);
7314 ha->logical_drive_info_dma_addr = dma_address;
7317 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7319 if (!ha->conf) {
7322 return ips_abort_init(ha, index);
7325 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7327 if (!ha->nvram) {
7330 return ips_abort_init(ha, index);
7333 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7335 if (!ha->subsys) {
7338 return ips_abort_init(ha, index);
7346 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7347 &ha->ioctl_busaddr);
7348 ha->ioctl_len = ips_ioctlsize;
7349 if (!ha->ioctl_data) {
7352 return ips_abort_init(ha, index);
7358 ips_setup_funclist(ha);
7360 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7362 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7364 ips_reset_morpheus(ha);
7372 if (!(*ha->func.isinit) (ha)) {
7373 if (!(*ha->func.init) (ha)) {
7379 return ips_abort_init(ha, index);
7399 ips_ha_t *ha;
7401 ha = ips_ha[index];
7404 if (!ha->active) {
7410 if (request_irq(ha->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7411 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7413 return ips_abort_init(ha, index);
7419 ha->max_cmds = 1;
7420 if (!ips_allocatescbs(ha)) {
7421 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7423 free_irq(ha->irq, ha);
7424 return ips_abort_init(ha, index);
7427 if (!ips_hainit(ha)) {
7428 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7430 free_irq(ha->irq, ha);
7431 return ips_abort_init(ha, index);
7434 ips_deallocatescbs(ha, 1);
7437 if (!ips_allocatescbs(ha)) {
7438 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7440 free_irq(ha->irq, ha);
7441 return ips_abort_init(ha, index);