Lines Matching refs:HCS_Base
175 if (ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & HOSTSTOP) /* Wait HOSTSTOP set */
188 if (ORC_RD(hcsp->HCS_Base, ORC_HSTUS) & RREADY) /* Wait READY set */
201 if (!(ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & SCSIRST)) /* Wait SCSIRST done */
214 if (!(ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & HDO)) /* Wait HDO off */
227 if ((*pData = ORC_RD(hcsp->HCS_Base, ORC_HSTUS)) & HDI)
243 ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_VERSION);
244 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
250 Version.cVersion[0] = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
251 ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData); /* Clear HDI */
255 Version.cVersion[1] = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
256 ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData); /* Clear HDI */
264 ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_SET_NVM); /* Write command */
265 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
269 ORC_WR(hcsp->HCS_Base + ORC_HDATA, address); /* Write address */
270 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
274 ORC_WR(hcsp->HCS_Base + ORC_HDATA, value); /* Write value */
275 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
287 ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_GET_NVM); /* Write command */
288 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
292 ORC_WR(hcsp->HCS_Base + ORC_HDATA, address); /* Write address */
293 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
299 *pDataIn = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
300 ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData); /* Clear HDI */
309 ORC_WR(hcsp->HCS_Base + ORC_PQUEUE, scbp->SCB_ScbIdx);
384 bData = ORC_RD(hcsp->HCS_Base, ORC_GCFG);
385 ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData | EEPRG); /* Enable EEPROM programming */
386 ORC_WR(hcsp->HCS_Base + ORC_EBIOSADR2, 0x00);
387 ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x00);
388 if (ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA) != 0x55) {
389 ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData); /* Disable EEPROM programming */
392 ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x01);
393 if (ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA) != 0xAA) {
394 ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData); /* Disable EEPROM programming */
397 ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST | DOWNLOAD); /* Enable SRAM programming */
400 ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x10);
401 *pData = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA); /* Read from BIOS */
402 ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x11);
403 *(pData + 1) = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA); /* Read from BIOS */
404 ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x12);
405 *(pData + 2) = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA); /* Read from BIOS */
406 ORC_WR(hcsp->HCS_Base + ORC_EBIOSADR2, *(pData + 2));
407 ORC_WRLONG(hcsp->HCS_Base + ORC_FWBASEADR, dData); /* Write FW address */
413 ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, wBIOSAddress);
414 *pData++ = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA); /* Read from BIOS */
416 ORC_WRLONG(hcsp->HCS_Base + ORC_RISCRAM, dData); /* Write every 4 bytes */
421 ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST | DOWNLOAD); /* Reset program count 0 */
426 ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, wBIOSAddress);
427 *pData++ = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA); /* Read from BIOS */
429 if (ORC_RDLONG(hcsp->HCS_Base, ORC_RISCRAM) != dData) {
430 ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST); /* Reset program to 0 */
431 ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData); /*Disable EEPROM programming */
437 ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST); /* Reset program to 0 */
438 ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData); /* Disable EEPROM programming */
450 /* Setup SCB HCS_Base and SCB Size registers */
451 ORC_WR(hcsp->HCS_Base + ORC_SCBSIZE, ORC_MAXQUEUE); /* Total number of SCBs */
452 /* SCB HCS_Base address 0 */
453 ORC_WRLONG(hcsp->HCS_Base + ORC_SCBBASE0, hcsp->HCS_physScbArray);
454 /* SCB HCS_Base address 1 */
455 ORC_WRLONG(hcsp->HCS_Base + ORC_SCBBASE1, hcsp->HCS_physScbArray);
494 ORC_WR(hcsp->HCS_Base + ORC_GIMSK, 0xFF); /* Disable all interrupt */
495 if (ORC_RD(hcsp->HCS_Base, ORC_HSTUS) & RREADY) { /* Orchid is ready */
498 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, DEVRST); /* Reset Host Adapter */
502 setup_SCBs(hcsp); /* Setup SCB HCS_Base and SCB Size registers */
503 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, 0); /* clear HOSTSTOP */
508 setup_SCBs(hcsp); /* Setup SCB HCS_Base and SCB Size registers */
511 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, DEVRST); /* Reset Host Adapter */
515 setup_SCBs(hcsp); /* Setup SCB HCS_Base and SCB Size registers */
516 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO); /* Do Hardware Reset & */
542 ORC_WR(hcsp->HCS_Base + ORC_GIMSK, 0xFB); /* enable RP FIFO interrupt */
562 ORC_WR(pHCB->HCS_Base + ORC_HCTRL, SCSIRST);
697 ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_ABORT_SCB); /* Write command */
698 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
702 ORC_WR(hcsp->HCS_Base + ORC_HDATA, pScb->SCB_ScbIdx); /* Write address */
703 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
709 bStatus = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
710 ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData); /* Clear HDI */
774 if (ORC_RD(hcsp->HCS_Base, ORC_RQUEUECNT) == 0) {
779 bScbIdx = ORC_RD(hcsp->HCS_Base, ORC_RQUEUE);
785 } while (ORC_RD(hcsp->HCS_Base, ORC_RQUEUECNT));
1080 pHCB->HCS_Base = port;
1112 shost->io_port = pHCB->HCS_Base;