Lines Matching refs:base
567 * Saves the length of all base address registers for the
580 u32 base;
613 // Figure out IO and memory base lengths
617 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
619 if (base) { // If this register is implemented
620 if (base & 0x01L) {
621 // IO base
622 // set base = amount of IO space requested
623 base = base & 0xFFFFFFFE;
624 base = (~base) + 1;
628 // memory base
629 base = base & 0xFFFFFFF0;
630 base = (~base) + 1;
635 base = 0x0L;
641 base;
644 } // End of base register loop
648 // Figure out IO and memory base lengths
652 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
654 if (base) { // If this register is implemented
655 if (base & 0x01L) {
656 // IO base
657 // base = amount of IO space requested
658 base = base & 0xFFFFFFFE;
659 base = (~base) + 1;
663 // memory base
664 // base = amount of memory space requested
665 base = base & 0xFFFFFFF0;
666 base = (~base) + 1;
671 base = 0x0L;
676 func->base_length[(cloop - 0x10) >> 2] = base;
679 } // End of base register loop
715 u32 base;
751 bus_node->base = secondary_bus;
757 // Save IO base and Limit registers
766 io_node->base = (b_base & 0xF0) << 8;
773 // Save memory base and Limit registers
782 mem_node->base = w_base << 16;
789 // Save prefetchable memory base and Limit registers
798 p_mem_node->base = w_base << 16;
804 // Figure out IO and memory base lengths
810 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
812 temp_register = base;
814 if (base) { // If this register is implemented
815 if (((base & 0x03L) == 0x01)
817 // IO base
819 temp_register = base & 0xFFFFFFFE;
827 io_node->base =
834 if (((base & 0x0BL) == 0x08)
836 // prefetchable memory base
837 temp_register = base & 0xFFFFFFF0;
845 p_mem_node->base = save_base & (~0x0FL);
851 if (((base & 0x0BL) == 0x00)
853 // prefetchable memory base
854 temp_register = base & 0xFFFFFFF0;
862 mem_node->base = save_base & (~0x0FL);
870 } // End of base register loop
872 // Figure out IO and memory base lengths
878 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
880 temp_register = base;
882 if (base) { // If this register is implemented
883 if (((base & 0x03L) == 0x01)
885 // IO base
887 temp_register = base & 0xFFFFFFFE;
895 io_node->base = save_base & (~0x01L);
901 if (((base & 0x0BL) == 0x08)
903 // prefetchable memory base
904 temp_register = base & 0xFFFFFFF0;
912 p_mem_node->base = save_base & (~0x0FL);
918 if (((base & 0x0BL) == 0x00)
920 // prefetchable memory base
921 temp_register = base & 0xFFFFFFF0;
929 mem_node->base = save_base & (~0x0FL);
937 } // End of base register loop
1002 // Check all the base Address Registers to make sure
1042 u32 base;
1112 // Figure out IO and memory base lengths
1116 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
1117 if (base) { // If this register is implemented
1118 if (base & 0x01L) {
1119 // IO base
1120 // set base = amount of IO space requested
1121 base = base & 0xFFFFFFFE;
1122 base = (~base) + 1;
1126 // memory base
1127 base = base & 0xFFFFFFF0;
1128 base = (~base) + 1;
1133 base = 0x0L;
1138 if (func->base_length[(cloop - 0x10) >> 2] != base)
1144 } // End of base register loop
1246 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n");
1303 // If we've got a valid IO base, use it
1312 io_node->base = io_base;
1315 dbg("found io_node(base, length) = %x, %x\n",
1316 io_node->base, io_node->length);
1327 // If we've got a valid memory base, use it
1334 mem_node->base = mem_base << 16;
1338 dbg("found mem_node(base, length) = %x, %x\n",
1339 mem_node->base, mem_node->length);
1350 // If we've got a valid prefetchable memory base, and
1351 // the base + length isn't greater than 0xFFFF
1358 p_mem_node->base = pre_mem_base << 16;
1361 dbg("found p_mem_node(base, length) = %x, %x\n",
1362 p_mem_node->base, p_mem_node->length);
1382 bus_node->base = secondary_bus;
1384 dbg("found bus_node(base, length) = %x, %x\n",
1385 bus_node->base, bus_node->length);