Lines Matching refs:base
105 hasr_read(u_long base)
107 return(inb(HASR(base)));
115 hacr_write(u_long base,
118 outb(hacr, HACR(base));
127 hacr_write_slow(u_long base,
130 hacr_write(base, hacr);
173 kio_addr_t base = dev->base_addr;
180 hacr_write(base, HACR_PWR_STAT | HACR_ROM_WEN);
196 hacr_write(base, HACR_DEFAULT);
280 mmc_out(u_long base,
287 while((count++ < 100) && (inb(HASR(base)) & HASR_MMI_BUSY))
290 outb((u_char)((o << 1) | MMR_MMI_WR), MMR(base));
291 outb(d, MMD(base));
300 mmc_write(u_long base,
309 mmc_out(base, --o, *(--b));
318 mmc_in(u_long base,
323 while((count++ < 100) && (inb(HASR(base)) & HASR_MMI_BUSY))
325 outb(o << 1, MMR(base)); /* Set the read address */
327 outb(0, MMD(base)); /* Required dummy write */
329 while((count++ < 100) && (inb(HASR(base)) & HASR_MMI_BUSY))
331 return (u_char) (inb(MMD(base))); /* Now do the actual read */
343 mmc_read(u_long base,
352 *(--b) = mmc_in(base, --o);
360 mmc_encr(u_long base) /* i/o port of the card */
364 temp = mmc_in(base, mmroff(0, mmr_des_avail));
377 fee_wait(u_long base, /* i/o port of the card */
384 (mmc_in(base, mmroff(0, mmr_fee_status)) & MMR_FEE_STATUS_BUSY))
393 fee_read(u_long base, /* i/o port of the card */
401 mmc_out(base, mmwoff(0, mmw_fee_addr), o + n - 1);
407 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_READ);
410 fee_wait(base, 10, 100);
413 *--b = ((mmc_in(base, mmroff(0, mmr_fee_data_h)) << 8) |
414 mmc_in(base, mmroff(0, mmr_fee_data_l)));
427 fee_write(u_long base, /* i/o port of the card */
437 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRREAD);
439 fee_wait(base, 10, 100);
443 mmc_in(base, mmroff(0, mmr_fee_data_h)),
444 mmc_in(base, mmroff(0, mmr_fee_data_l)));
448 mmc_out(base, mmwoff(0, mmw_fee_addr), MMW_FEE_ADDR_EN);
449 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PREN);
451 fee_wait(base, 10, 100);
454 mmc_out(base, mmwoff(0, mmw_fee_addr), o + n);
455 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRWRITE);
458 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRCLEAR);
461 fee_wait(base, 10, 100);
465 mmc_out(base, mmwoff(0, mmw_fee_addr), MMW_FEE_ADDR_EN);
466 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_WREN);
468 fee_wait(base, 10, 100);
471 mmc_out(base, mmwoff(0, mmw_fee_addr), o + n - 1);
477 mmc_out(base, mmwoff(0, mmw_fee_data_h), (*--b) >> 8);
478 mmc_out(base, mmwoff(0, mmw_fee_data_l), *b & 0xFF);
481 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_WRITE);
485 fee_wait(base, 10, 100);
489 mmc_out(base, mmwoff(0, mmw_fee_addr), MMW_FEE_ADDR_DS);
490 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_WDS);
492 fee_wait(base, 10, 100);
496 mmc_out(base, mmwoff(0, mmw_fee_addr), 0x00);
497 mmc_out(base, mmwoff(0, mmw_fee_ctrl), MMW_FEE_CTRL_PRWRITE);
499 fee_wait(base, 10, 100);
731 kio_addr_t base = lp->dev->base_addr;
751 mmc_write(base, (char *)&m.w.mmw_netw_id_l - (char *)&m, (unsigned char *)&m.w.mmw_netw_id_l, 2);
844 kio_addr_t base = dev->base_addr;
857 outb(OP0_NOP | CR0_STATUS_3, LCCR(base));
858 status = inb(LCSR(base));
873 outb(cmd, LCCR(base));
891 outb(CR0_STATUS_0 | OP0_NOP, LCCR(base));
892 status = inb(LCSR(base));
898 outb(CR0_INT_ACK | OP0_NOP, LCCR(base));
968 kio_addr_t base = dev->base_addr;
977 outb(ring_ptr & 0xff, PIORL(base));
978 outb(((ring_ptr >> 8) & PIORH_MASK), PIORH(base));
986 insb(PIOP(base), buf_ptr, chunk_len);
1134 kio_addr_t base = dev->base_addr;
1139 if(hasr_read(base) & HASR_NO_CLK)
1149 mmc_out(base, mmwoff(0, mmw_freeze), 1);
1150 mmc_read(base, 0, (u_char *)&m, sizeof(m));
1151 mmc_out(base, mmwoff(0, mmw_freeze), 0);
1312 kio_addr_t base = dev->base_addr;
1332 dev->name, base, dev->irq);
1343 if(!(mmc_in(base, mmroff(0, mmr_fee_status)) &
1349 fee_read(base, 0x00 /* 1st area - frequency... */,
1547 wv_set_frequency(u_long base, /* i/o port of the card */
1583 fee_read(base, 0x71 /* frequency table */,
1625 fee_read(base, 0x00,
1629 fee_read(base, 0x60,
1633 fee_read(base, 0x6B - (power_band >> 1),
1671 fee_write(base, 0x00,
1675 fee_write(base, 0x60,
1681 fee_read(base, 0x00,
1685 fee_read(base, 0x60,
1702 mmc_out(base, mmwoff(0, mmw_fee_addr), 0x0F);
1703 mmc_out(base, mmwoff(0, mmw_fee_ctrl),
1707 fee_wait(base, 100, 100);
1711 mmc_out(base, mmwoff(0, mmw_fee_addr), 0x61);
1712 mmc_out(base, mmwoff(0, mmw_fee_ctrl),
1716 fee_wait(base, 100, 100);
1744 wv_frequency_list(u_long base, /* i/o port of the card */
1755 fee_read(base, 0x71 /* frequency table */,
1865 kio_addr_t base = dev->base_addr;
1888 mmc_write(base,
1892 mmc_out(base, mmwoff(0, mmw_loopt_sel), 0x00);
1903 mmc_out(base, mmwoff(0, mmw_loopt_sel),
1955 kio_addr_t base = dev->base_addr;
1964 if (!(mmc_in(base, mmroff(0, mmr_fee_status)) &
1966 ret = wv_set_frequency(base, &(wrqu->freq));
1985 kio_addr_t base = dev->base_addr;
1996 if (!(mmc_in(base, mmroff(0, mmr_fee_status)) &
2001 fee_read(base, 0x00, &freq, 1);
2031 kio_addr_t base = dev->base_addr;
2049 mmc_out(base, mmwoff(0, mmw_thr_pre_set),
2097 kio_addr_t base = dev->base_addr;
2107 if (!mmc_encr(base)) {
2130 mmc_out(base, mmwoff(0, mmw_encr_enable),
2132 mmc_write(base, mmwoff(0, mmw_encr_key),
2146 mmc_out(base, mmwoff(0, mmw_encr_enable), 0);
2167 kio_addr_t base = dev->base_addr;
2177 if (!mmc_encr(base)) {
2192 wrqu->encoding.flags |= mmc_encr(base);
2386 kio_addr_t base = dev->base_addr;
2429 if (!(mmc_in(base, mmroff(0, mmr_fee_status)) &
2432 range->num_frequency = wv_frequency_list(base, range->freq,
2438 if (mmc_encr(base)) {
2462 kio_addr_t base = dev->base_addr;
2476 mmc_out(base, mmwoff(0, mmw_quality_thr),
2738 kio_addr_t base = dev->base_addr;
2754 mmc_out(base, mmwoff(0, mmw_freeze), 1);
2756 mmc_read(base, mmroff(0, mmr_dce_status), &m.mmr_dce_status, 1);
2757 mmc_read(base, mmroff(0, mmr_wrong_nwid_l), &m.mmr_wrong_nwid_l, 2);
2758 mmc_read(base, mmroff(0, mmr_thr_pre_set), &m.mmr_thr_pre_set, 4);
2760 mmc_out(base, mmwoff(0, mmw_freeze), 0);
2801 kio_addr_t base = dev->base_addr;
2806 outb(rp & 0xff, PIORL(base));
2807 outb(((rp >> 8) & PIORH_MASK), PIORH(base));
2808 len = inb(PIOP(base));
2809 len |= inb(PIOP(base)) << 8;
2962 kio_addr_t base = dev->base_addr;
2978 outb(CR0_STATUS_2 | OP0_NOP, LCCR(base));
2979 i593_rfp = inb(LCSR(base));
2980 i593_rfp |= inb(LCSR(base)) << 8;
2988 newrfp = inb(RPLL(base));
2989 newrfp |= inb(RPLH(base)) << 8;
3069 outb(OP0_SWIT_TO_PORT_1 | CR0_CHNL, LCCR(base));
3070 outb(CR1_STOP_REG_UPDATE | (lp->stop >> RX_SIZE_SHIFT), LCCR(base));
3071 outb(OP1_SWIT_TO_PORT_0, LCCR(base));
3099 kio_addr_t base = dev->base_addr;
3111 outb(xmtdata_base & 0xff, PIORL(base));
3112 outb(((xmtdata_base >> 8) & PIORH_MASK) | PIORH_SEL_TX, PIORH(base));
3113 outb(clen & 0xff, PIOP(base)); /* lsb */
3114 outb(clen >> 8, PIOP(base)); /* msb */
3117 outsb(PIOP(base), buf, clen);
3120 outb(OP0_NOP, PIOP(base));
3122 outb(OP0_NOP, PIOP(base));
3125 hacr_write_slow(base, HACR_PWR_STAT | HACR_TX_DMA_RESET);
3126 hacr_write(base, HACR_DEFAULT);
3220 kio_addr_t base = dev->base_addr;
3346 mmc_write(base, 0, (u_char *)&m, sizeof(m));
3362 if(!(mmc_in(base, mmroff(0, mmr_fee_status)) &
3371 mmc_write(base, (char *)&m.mmw_fee_ctrl - (char *)&m,
3375 fee_wait(base, 100, 100);
3379 mmc_read(base, (char *)&m.mmw_fee_data_l - (char *)&m,
3393 mmc_write(base, (char *)&m.mmw_fee_ctrl - (char *)&m,
3414 kio_addr_t base = dev->base_addr;
3435 outb(OP0_NOP | CR0_STATUS_3, LCCR(base));
3436 status = inb(LCSR(base));
3444 outb(OP0_NOP | CR0_STATUS_3, LCCR(base));
3445 status = inb(LCSR(base));
3477 kio_addr_t base = dev->base_addr;
3499 outb(OP0_SWIT_TO_PORT_1 | CR0_CHNL, LCCR(base));
3502 outb(OP1_RESET_RING_MNGMT, LCCR(base));
3506 outb(CR1_STOP_REG_UPDATE | (lp->stop >> RX_SIZE_SHIFT), LCCR(base));
3507 outb(OP1_INT_ENABLE, LCCR(base));
3508 outb(OP1_SWIT_TO_PORT_0, LCCR(base));
3511 hacr_write_slow(base, HACR_PWR_STAT | HACR_TX_DMA_RESET);
3512 hacr_write_slow(base, HACR_DEFAULT);
3527 outb(OP0_NOP | CR0_STATUS_3, LCCR(base));
3528 status = inb(LCSR(base));
3556 kio_addr_t base = dev->base_addr;
3643 outb(TX_BASE & 0xff, PIORL(base));
3644 outb(((TX_BASE >> 8) & PIORH_MASK) | PIORH_SEL_TX, PIORH(base));
3645 outb(sizeof(struct i82593_conf_block) & 0xff, PIOP(base)); /* lsb */
3646 outb(sizeof(struct i82593_conf_block) >> 8, PIOP(base)); /* msb */
3647 outsb(PIOP(base), (char *) &cfblk, sizeof(struct i82593_conf_block));
3650 hacr_write_slow(base, HACR_PWR_STAT | HACR_TX_DMA_RESET);
3651 hacr_write(base, HACR_DEFAULT);
3657 outb(TX_BASE & 0xff, PIORL(base));
3658 outb(((TX_BASE >> 8) & PIORH_MASK) | PIORH_SEL_TX, PIORH(base));
3659 outb(WAVELAN_ADDR_SIZE, PIOP(base)); /* byte count lsb */
3660 outb(0, PIOP(base)); /* byte count msb */
3661 outsb(PIOP(base), &dev->dev_addr[0], WAVELAN_ADDR_SIZE);
3664 hacr_write_slow(base, HACR_PWR_STAT | HACR_TX_DMA_RESET);
3665 hacr_write(base, HACR_DEFAULT);
3693 outb(TX_BASE & 0xff, PIORL(base));
3694 outb(((TX_BASE >> 8) & PIORH_MASK) | PIORH_SEL_TX, PIORH(base));
3695 outb(addrs_len & 0xff, PIOP(base)); /* byte count lsb */
3696 outb((addrs_len >> 8), PIOP(base)); /* byte count msb */
3698 outsb(PIOP(base), dmi->dmi_addr, dmi->dmi_addrlen);
3701 hacr_write_slow(base, HACR_PWR_STAT | HACR_TX_DMA_RESET);
3702 hacr_write(base, HACR_DEFAULT);
3793 kio_addr_t base = dev->base_addr;
3822 hacr_write_slow(base, HACR_RESET);
3823 hacr_write(base, HACR_DEFAULT);
3826 if(hasr_read(base) & HASR_NO_CLK)
3846 outb(OP0_RESET, LCCR(base));
4079 kio_addr_t base;
4088 base = dev->base_addr;
4111 outb(CR0_STATUS_0 | OP0_NOP, LCCR(base));
4112 status0 = inb(LCSR(base));
4143 outb(CR0_INT_ACK | OP0_NOP, LCCR(base));
4174 outb(CR0_INT_ACK | OP0_NOP, LCCR(base));
4196 tx_status = inb(LCSR(base));
4197 tx_status |= (inb(LCSR(base)) << 8);
4204 rcv_bytes = inb(LCSR(base));
4205 rcv_bytes |= (inb(LCSR(base)) << 8);
4206 status3 = inb(LCSR(base));
4285 outb(CR0_INT_ACK | OP0_NOP, LCCR(base)); /* Acknowledge the interrupt */
4293 outb(CR0_INT_ACK | OP0_NOP, LCCR(base)); /* Acknowledge the interrupt */
4338 kio_addr_t base = dev->base_addr;
4354 outb(OP0_ABORT, LCCR(base));
4414 kio_addr_t base = dev->base_addr;
4422 if(hasr_read(base) & HASR_NO_CLK)
4425 hacr_write(base, HACR_DEFAULT);
4428 if(hasr_read(base) & HASR_NO_CLK)
4468 kio_addr_t base = dev->base_addr;
4501 hacr_write(base, HACR_DEFAULT & (~HACR_PWR_STAT));