Lines Matching refs:sbtmstatelow
1173 u32 sbtmstatelow;
1177 /* fetch sbtmstatelow from core information registers */
1178 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1181 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1184 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1185 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1187 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1190 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1191 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1215 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1220 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1224 sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1227 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1238 u32 sbtmstatelow;
1247 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1251 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1266 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1269 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1272 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1273 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1316 u32 sbtmstatelow;
1320 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1321 sbtmstatelow &= 0xDFF5FFFF;
1322 sbtmstatelow |= 0x000A0000;
1323 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1325 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1326 sbtmstatelow &= 0xFFF5FFFF;
1327 sbtmstatelow |= 0x00080000;
1328 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
3458 u32 sbtmstatelow;
3460 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
3461 sbtmstatelow |= BCM43xx_SBTMSTATELOW_G_MODE_ENABLE;
3462 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);