Lines Matching defs:define
120 #define DRV_NAME "dscc4"
137 int define;
157 #define DUMMY_SKB_SIZE 64
158 #define TX_LOW 8
159 #define TX_RING_SIZE 32
160 #define RX_RING_SIZE 32
161 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
162 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
163 #define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
164 #define TX_TIMEOUT (HZ/10)
165 #define DSCC4_HZ_MAX 33000000
166 #define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
167 #define dev_per_card 4
168 #define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
170 #define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
171 #define TO_SIZE(state) (((state) >> 16) & 0x1fff)
178 #define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
179 #define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
180 #define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
181 #define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
238 #define GCMDR 0x00
239 #define GSTAR 0x04
240 #define GMODE 0x08
241 #define IQLENR0 0x0C
242 #define IQLENR1 0x10
243 #define IQRX0 0x14
244 #define IQTX0 0x24
245 #define IQCFG 0x3c
246 #define FIFOCR1 0x44
247 #define FIFOCR2 0x48
248 #define FIFOCR3 0x4c
249 #define FIFOCR4 0x34
250 #define CH0CFG 0x50
251 #define CH0BRDA 0x54
252 #define CH0BTDA 0x58
253 #define CH0FRDA 0x98
254 #define CH0FTDA 0xb0
255 #define CH0LRDA 0xc8
256 #define CH0LTDA 0xe0
259 #define SCC_START 0x0100
260 #define SCC_OFFSET 0x80
261 #define CMDR 0x00
262 #define STAR 0x04
263 #define CCR0 0x08
264 #define CCR1 0x0c
265 #define CCR2 0x10
266 #define BRR 0x2C
267 #define RLCR 0x40
268 #define IMR 0x54
269 #define ISR 0x58
271 #define GPDIR 0x0400
272 #define GPDATA 0x0404
273 #define GPIM 0x0408
276 #define EncodingMask 0x00700000
277 #define CrcMask 0x00000003
279 #define IntRxScc0 0x10000000
280 #define IntTxScc0 0x01000000
282 #define TxPollCmd 0x00000400
283 #define RxActivate 0x08000000
284 #define MTFi 0x04000000
285 #define Rdr 0x00400000
286 #define Rdt 0x00200000
287 #define Idr 0x00100000
288 #define Idt 0x00080000
289 #define TxSccRes 0x01000000
290 #define RxSccRes 0x00010000
291 #define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
292 #define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
294 #define Ccr0ClockMask 0x0000003f
295 #define Ccr1LoopMask 0x00000200
296 #define IsrMask 0x000fffff
297 #define BrrExpMask 0x00000f00
298 #define BrrMultMask 0x0000003f
299 #define EncodingMask 0x00700000
300 #define Hold 0x40000000
301 #define SccBusy 0x10000000
302 #define PowerUp 0x80000000
303 #define Vis 0x00001000
304 #define FrameOk (FrameVfr | FrameCrc)
305 #define FrameVfr 0x80
306 #define FrameRdo 0x40
307 #define FrameCrc 0x20
308 #define FrameRab 0x10
309 #define FrameAborted 0x00000200
310 #define FrameEnd 0x80000000
311 #define DataComplete 0x40000000
312 #define LengthCheck 0x00008000
313 #define SccEvt 0x02000000
314 #define NoAck 0x00000200
315 #define Action 0x00000001
316 #define HiDesc 0x20000000
319 #define RxEvt 0xf0000000
320 #define TxEvt 0x0f000000
321 #define Alls 0x00040000
322 #define Xdu 0x00010000
323 #define Cts 0x00004000
324 #define Xmr 0x00002000
325 #define Xpr 0x00001000
326 #define Rdo 0x00000080
327 #define Rfs 0x00000040
328 #define Cd 0x00000004
329 #define Rfo 0x00000002
330 #define Flex 0x00000001
333 #define Cfg 0x00200000
334 #define Hi 0x00040000
335 #define Fi 0x00020000
336 #define Err 0x00010000
337 #define Arf 0x00000002
338 #define ArAck 0x00000001
341 #define Ready 0x00000000
342 #define NeedIDR 0x00000001
343 #define NeedIDT 0x00000002
344 #define RdoSet 0x00000004
345 #define FakeReset 0x00000008
349 #define EventsMask 0xfffeef7f
351 #define EventsMask 0xfffa8f7a
999 #define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1272 for (i = 0; p[i].define != -1; i++) {
1273 if (value == p[i].define)
1276 if (p[i].define == -1)