Lines Matching refs:EISA
39 ** EISA Register Address Map
41 #define EISA_ID iobase+0x0c80 /* EISA ID Registers */
42 #define EISA_ID0 iobase+0x0c80 /* EISA ID Register 0 */
43 #define EISA_ID1 iobase+0x0c81 /* EISA ID Register 1 */
44 #define EISA_ID2 iobase+0x0c82 /* EISA ID Register 2 */
45 #define EISA_ID3 iobase+0x0c83 /* EISA ID Register 3 */
46 #define EISA_CR iobase+0x0c84 /* EISA Control Register */
47 #define EISA_REG0 iobase+0x0c88 /* EISA Configuration Register 0 */
48 #define EISA_REG1 iobase+0x0c89 /* EISA Configuration Register 1 */
49 #define EISA_REG2 iobase+0x0c8a /* EISA Configuration Register 2 */
50 #define EISA_REG3 iobase+0x0c8f /* EISA Configuration Register 3 */
54 ** PCI/EISA Configuration Registers Address Map
69 ** EISA Configuration Register 0 bit definitions
71 #define ER0_BSW 0x80 /* EISA Bus Slave Width, 1: 32 bits */
72 #define ER0_BMW 0x40 /* EISA Bus Master Width, 1: 32 bits */
73 #define ER0_EPT 0x20 /* EISA PREEMPT Time, 0: 23 BCLKs */
80 ** EISA Configuration Register 1 bit definitions
87 ** EISA Configuration Register 2 bit definitions
93 ** EISA Configuration Register 3 bit definitions
861 #define EISA 1