Lines Matching refs:adap
54 struct adapter *adap = mac->adapter;
57 t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
61 t3_read_reg(adap, ctrl);
65 t3_set_reg_field(adap, ctrl, clear[i], 0);
99 struct adapter *adap = mac->adapter;
102 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
103 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
105 t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft);
106 t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft,
108 uses_xaui(adap) ? 0 : F_RXSTRFRWRD);
110 if (uses_xaui(adap)) {
111 if (adap->params.rev == 0) {
112 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
114 if (t3_wait_op_done(adap, A_XGM_SERDES_STATUS1 + oft,
116 CH_ERR(adap,
121 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
128 if (is_10G(adap))
130 else if (uses_xaui(adap))
134 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
135 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
136 if ((val & F_PCS_RESET_) && adap->params.rev) {
147 struct adapter *adap = mac->adapter;
152 t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
154 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
156 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
157 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
162 if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
164 CH_ERR(adap, "MAC %d Rx fifo drain failed\n",
169 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0);
170 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
173 if (is_10G(adap))
175 else if (uses_xaui(adap))
179 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
180 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
181 if ((val & F_PCS_RESET_) && adap->params.rev) {
185 t3_write_reg(adap, A_XGM_RX_CFG + oft,
190 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE);
192 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE);
273 struct adapter *adap = mac->adapter;
276 val = t3_read_reg(adap, A_XGM_RX_CFG + oft) & ~F_COPYALLFRAMES;
279 t3_write_reg(adap, A_XGM_RX_CFG + oft, val);
301 t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);
302 t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);
318 struct adapter *adap = mac->adapter;
327 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
338 if (adap->params.rev == T3_REV_B2 &&
339 (t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
341 v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
342 t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
346 if (t3_wait_op_done(adap,
350 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
354 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
355 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
358 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
366 v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
373 t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
376 thres = (adap->params.vpd.cclk * 1000) / 15625;
378 if (is_10G(adap))
382 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
386 if (adap->params.rev > 0)
387 t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
389 t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
397 struct adapter *adap = mac->adapter;
414 t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
418 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
422 t3_read_reg(adap,
425 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
427 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
435 struct adapter *adap = mac->adapter;
440 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
441 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
442 t3_write_reg(adap, A_TP_PIO_DATA, 0xc0ede401);
443 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
444 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
446 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
448 mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
450 mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
454 mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
461 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
468 struct adapter *adap = mac->adapter;
472 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
473 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
474 t3_write_reg(adap, A_TP_PIO_DATA, 0xc000001f);
475 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
476 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
483 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
485 if (is_10G(adap))
487 else if (uses_xaui(adap))
498 struct adapter *adap = mac->adapter;
511 tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
515 t3_write_reg(adap, A_TP_PIO_ADDR,
517 tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
545 rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
564 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
565 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
566 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen);
567 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */