Lines Matching defs:int_status
424 unsigned long int_status, reg_data;
436 int_status =
438 if (int_status & BIG_SUR_GE_EIR_XMIT_LFIFO_FULL_MASK) {
494 unsigned long int_status, reg_data;
509 int_status =
511 if (int_status & BIG_SUR_GE_EIR_RECV_LFIFO_EMPTY_MASK) {
577 unsigned long int_status;
579 int_status =
581 if (int_status & BIG_SUR_GE_IPIF_EMAC_MASK)
584 if (int_status & BIG_SUR_GE_IPIF_RECV_FIFO_MASK)
587 if (int_status & BIG_SUR_GE_IPIF_SEND_FIFO_MASK)
590 if (int_status & XIIF_V123B_ERROR_MASK)
623 unsigned long int_status;
626 int_status =
629 int_status);
632 if (int_status & BIG_SUR_GE_EIR_RECV_DONE_MASK) {
639 if (int_status & BIG_SUR_GE_EIR_XMIT_DONE_MASK) {
648 big_sur_ge_check_mac_error(emac, int_status);
663 unsigned long int_status;
665 int_status = big_sur_ge_get_intr_status(&emac->recv_channel);
666 if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
715 big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
717 if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
721 big_sur_ge_set_intr_status(&emac->recv_channel, int_status);
729 unsigned long int_status;
731 int_status = big_sur_ge_get_intr_status(&emac->send_channel);
733 if (int_status & (BIG_SUR_GE_IXR_PKT_THRESHOLD_MASK |
778 big_sur_ge_set_intr_status(&emac->send_channel, int_status);
779 if (int_status & BIG_SUR_GE_IXR_DMA_ERROR_MASK) {
783 big_sur_ge_set_intr_status(&emac->send_channel, int_status);
792 unsigned long int_status)
794 if (int_status & (BIG_SUR_GE_EIR_RECV_DFIFO_OVER_MASK |