Lines Matching refs:ucb
39 * @ucb: UCB1x00 structure describing chip
53 void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out)
57 spin_lock_irqsave(&ucb->io_lock, flags);
58 ucb->io_dir |= out;
59 ucb->io_dir &= ~in;
61 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
62 spin_unlock_irqrestore(&ucb->io_lock, flags);
67 * @ucb: UCB1x00 structure describing chip
81 void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear)
85 spin_lock_irqsave(&ucb->io_lock, flags);
86 ucb->io_out |= set;
87 ucb->io_out &= ~clear;
89 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
90 spin_unlock_irqrestore(&ucb->io_lock, flags);
95 * @ucb: UCB1x00 structure describing chip
105 unsigned int ucb1x00_io_read(struct ucb1x00 *ucb)
107 return ucb1x00_reg_read(ucb, UCB_IO_DATA);
121 * @ucb: UCB1x00 structure describing chip
135 void ucb1x00_adc_enable(struct ucb1x00 *ucb)
137 down(&ucb->adc_sem);
139 ucb->adc_cr |= UCB_ADC_ENA;
141 ucb1x00_enable(ucb);
142 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
147 * @ucb: UCB1x00 structure describing chip
161 unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync)
168 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel);
169 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START);
172 val = ucb1x00_reg_read(ucb, UCB_ADC_DATA);
185 * @ucb: UCB1x00 structure describing chip
189 void ucb1x00_adc_disable(struct ucb1x00 *ucb)
191 ucb->adc_cr &= ~UCB_ADC_ENA;
192 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
193 ucb1x00_disable(ucb);
195 up(&ucb->adc_sem);
208 struct ucb1x00 *ucb = devid;
212 ucb1x00_enable(ucb);
213 isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
214 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
215 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
217 for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++)
220 ucb1x00_disable(ucb);
227 * @ucb: UCB1x00 structure describing chip
242 int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid)
248 irq = ucb->irq_handler + idx;
251 spin_lock_irq(&ucb->lock);
257 spin_unlock_irq(&ucb->lock);
264 * @ucb: UCB1x00 structure describing chip
272 void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
277 spin_lock_irqsave(&ucb->lock, flags);
279 ucb1x00_enable(ucb);
281 ucb->irq_ris_enbl |= 1 << idx;
282 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
285 ucb->irq_fal_enbl |= 1 << idx;
286 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
288 ucb1x00_disable(ucb);
289 spin_unlock_irqrestore(&ucb->lock, flags);
295 * @ucb: UCB1x00 structure describing chip
301 void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
306 spin_lock_irqsave(&ucb->lock, flags);
308 ucb1x00_enable(ucb);
310 ucb->irq_ris_enbl &= ~(1 << idx);
311 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
314 ucb->irq_fal_enbl &= ~(1 << idx);
315 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
317 ucb1x00_disable(ucb);
318 spin_unlock_irqrestore(&ucb->lock, flags);
324 * @ucb: UCB1x00 structure describing chip
335 int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid)
343 irq = ucb->irq_handler + idx;
346 spin_lock_irq(&ucb->lock);
348 ucb->irq_ris_enbl &= ~(1 << idx);
349 ucb->irq_fal_enbl &= ~(1 << idx);
351 ucb1x00_enable(ucb);
352 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
353 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
354 ucb1x00_disable(ucb);
360 spin_unlock_irq(&ucb->lock);
368 static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv)
375 dev->ucb = ucb;
381 list_add(&dev->dev_node, &ucb->devs);
417 static int ucb1x00_detect_irq(struct ucb1x00 *ucb)
430 ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
431 ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
432 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
433 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
438 ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
439 ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
444 while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0);
445 ucb1x00_reg_write(ucb, UCB_ADC_CR, 0);
450 ucb1x00_reg_write(ucb, UCB_IE_RIS, 0);
451 ucb1x00_reg_write(ucb, UCB_IE_FAL, 0);
452 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
453 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
463 struct ucb1x00 *ucb = classdev_to_ucb1x00(dev);
464 kfree(ucb);
474 struct ucb1x00 *ucb;
487 ucb = kmalloc(sizeof(struct ucb1x00), GFP_KERNEL);
489 if (!ucb)
492 memset(ucb, 0, sizeof(struct ucb1x00));
494 ucb->cdev.class = &ucb1x00_class;
495 ucb->cdev.dev = &mcp->attached_device;
496 strlcpy(ucb->cdev.class_id, "ucb1x00", sizeof(ucb->cdev.class_id));
498 spin_lock_init(&ucb->lock);
499 spin_lock_init(&ucb->io_lock);
500 sema_init(&ucb->adc_sem, 1);
502 ucb->id = id;
503 ucb->mcp = mcp;
504 ucb->irq = ucb1x00_detect_irq(ucb);
505 if (ucb->irq == NO_IRQ) {
511 ret = request_irq(ucb->irq, ucb1x00_irq, IRQF_TRIGGER_RISING,
512 "UCB1x00", ucb);
515 ucb->irq, ret);
519 mcp_set_drvdata(mcp, ucb);
521 ret = class_device_register(&ucb->cdev);
525 INIT_LIST_HEAD(&ucb->devs);
527 list_add(&ucb->node, &ucb1x00_devices);
529 ucb1x00_add_dev(ucb, drv);
535 free_irq(ucb->irq, ucb);
537 kfree(ucb);
546 struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
550 list_del(&ucb->node);
551 list_for_each_safe(l, n, &ucb->devs) {
557 free_irq(ucb->irq, ucb);
558 class_device_unregister(&ucb->cdev);
563 struct ucb1x00 *ucb;
568 list_for_each_entry(ucb, &ucb1x00_devices, node) {
569 ucb1x00_add_dev(ucb, drv);
590 struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
594 list_for_each_entry(dev, &ucb->devs, dev_node) {
604 struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
608 list_for_each_entry(dev, &ucb->devs, dev_node) {