Lines Matching defs:hdw
27 #include "pvrusb2-hdw-internal.h"
41 static int pvr2_encoder_write_words(struct pvr2_hdw *hdw,
63 memset(hdw->cmd_buffer,0,sizeof(hdw->cmd_buffer));
65 hdw->cmd_buffer[bAddr++] = FX2CMD_MEM_WRITE_DWORD;
68 hdw->cmd_buffer[bAddr+6] = (addr & 0xffu);
69 hdw->cmd_buffer[bAddr+5] = ((addr>>8) & 0xffu);
70 hdw->cmd_buffer[bAddr+4] = ((addr>>16) & 0xffu);
71 PVR2_DECOMPOSE_LE(hdw->cmd_buffer, bAddr,data[idx]);
74 ret = pvr2_send_request(hdw,
75 hdw->cmd_buffer,1+(chunkCnt*7),
87 static int pvr2_encoder_read_words(struct pvr2_hdw *hdw,
109 hdw->cmd_buffer[0] =
112 hdw->cmd_buffer[1] = 0;
113 hdw->cmd_buffer[2] = 0;
114 hdw->cmd_buffer[3] = 0;
115 hdw->cmd_buffer[4] = 0;
116 hdw->cmd_buffer[5] = ((offs>>16) & 0xffu);
117 hdw->cmd_buffer[6] = ((offs>>8) & 0xffu);
118 hdw->cmd_buffer[7] = (offs & 0xffu);
119 ret = pvr2_send_request(hdw,
120 hdw->cmd_buffer,8,
121 hdw->cmd_buffer,
126 data[idx] = PVR2_COMPOSE_LE(hdw->cmd_buffer,idx*4);
156 struct pvr2_hdw *hdw = (struct pvr2_hdw *)ctxt;
210 LOCK_TAKE(hdw->ctl_lock); do {
226 ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,idx);
229 ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
234 ret = pvr2_encoder_read_words(hdw,MBOX_BASE,rdData,
289 ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
292 } while(0); LOCK_GIVE(hdw->ctl_lock);
298 static int pvr2_encoder_vcmd(struct pvr2_hdw *hdw, int cmd,
321 return pvr2_encoder_cmd(hdw,cmd,args,0,data);
327 static int pvr2_encoder_prep_config(struct pvr2_hdw *hdw)
347 switch (hdw->hdw_type) {
352 ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 3,
355 ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 8,0,0,0);
358 ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 0,3,0,0);
359 ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4,15,0,0,0);
364 int pvr2_encoder_configure(struct pvr2_hdw *hdw)
370 hdw->enc_ctl_state.port = CX2341X_PORT_STREAMING;
371 hdw->enc_ctl_state.width = hdw->res_hor_val;
372 hdw->enc_ctl_state.height = hdw->res_ver_val;
373 hdw->enc_ctl_state.is_50hz = ((hdw->std_mask_cur & V4L2_STD_525_60) ?
378 ret |= pvr2_encoder_prep_config(hdw);
382 if (hdw->hdw_type == PVR2_HDW_TYPE_24XXX) {
388 hdw,CX2341X_ENC_SET_NUM_VSYNC_LINES, 2,
393 hdw,CX2341X_ENC_SET_EVENT_NOTIFICATION, 4,
397 hdw,CX2341X_ENC_SET_VBI_LINE, 5,
406 ret = cx2341x_update(hdw,pvr2_encoder_cmd,
407 (hdw->enc_cur_valid ? &hdw->enc_cur_state : NULL),
408 &hdw->enc_ctl_state);
418 hdw, CX2341X_ENC_INITIALIZE_INPUT, 0);
426 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
427 memcpy(&hdw->enc_cur_state,&hdw->enc_ctl_state,
429 hdw->enc_cur_valid = !0;
434 int pvr2_encoder_start(struct pvr2_hdw *hdw)
439 pvr2_write_register(hdw, 0x0048, 0xbfffffff);
442 pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000481);
443 pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000000);
445 pvr2_encoder_vcmd(hdw,CX2341X_ENC_MUTE_VIDEO,1,
446 hdw->input_val == PVR2_CVAL_INPUT_RADIO ? 1 : 0);
448 switch (hdw->config) {
450 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
454 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
458 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
463 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_RUN);
468 int pvr2_encoder_stop(struct pvr2_hdw *hdw)
473 pvr2_write_register(hdw, 0x0048, 0xffffffff);
475 switch (hdw->config) {
477 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
481 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
485 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
493 pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000401);
494 pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000000);
497 hdw->subsys_enabled_mask &= ~(1<<PVR2_SUBSYS_B_ENC_RUN);