Lines Matching refs:bpl
90 unsigned int bpl, unsigned int padding,
107 if (bpl <= sg_dma_len(sg)-offset) {
109 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
111 offset+=bpl;
114 todo = bpl;
141 unsigned int bpl, unsigned int padding, unsigned int lines)
155 can cause next bpl to start close to a page border. First DMA
157 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
166 bpl, padding, lines);
169 bpl, padding, lines);
178 struct scatterlist *sglist, unsigned int bpl,
189 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
196 rp = cx88_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
352 unsigned int bpl, u32 risc)
357 bpl = (bpl + 7) & ~7; /* alignment */
359 lines = ch->fifo_size / bpl;
366 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
380 cx_write(ch->cnt1_reg, (bpl >> 3) -1);
383 dprintk(2,"sram setup %s: bpl=%d lines=%d\n", ch->name, bpl, lines);
801 int bpl = cx88_sram_channels[SRAM_CH25].fifo_size/4;
808 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], bpl, 0);
809 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], bpl, 0);
811 cx_write(MO_AUDD_LNGTH, bpl); /* fifo bpl size */
812 cx_write(MO_AUDR_LNGTH, bpl); /* fifo bpl size */