Lines Matching refs:tda1004x_write_byteI
129 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
190 return tda1004x_write_byteI(state, reg, val);
202 result = tda1004x_write_byteI(state, reg + i, buf[i]);
251 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
282 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
283 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
295 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
296 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
308 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
309 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
330 tda1004x_write_byteI(state, dspCodeCounterReg, 0);
376 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
439 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
442 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
445 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
449 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
452 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
455 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
457 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
461 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
462 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
465 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
466 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
469 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
470 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
473 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
474 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
490 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
493 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0x80);
498 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
591 return tda1004x_write_byteI(state, buf[0], buf[1]);
614 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
615 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
618 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
637 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
638 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer
642 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
646 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
650 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
654 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
655 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
656 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
668 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
670 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
671 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
672 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
673 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
674 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
675 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
676 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
677 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
1175 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);