Lines Matching defs:ireg
89 rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u_char *msg)
94 if (msg && ireg->clsb) {
96 for (i=1; i < ireg->clsb; i++)
102 i = ireg->clsb;
105 t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);
106 QuickHex(t, &msg[ireg->clsb-i], (i>64) ? 64:i);
118 get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg)
120 ireg->iis = cs->BC_Read_Reg(cs, 1, ISAR_IIS);
121 ireg->cmsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_H);
122 ireg->clsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_L);
125 debugl1(cs, "irq_stat(%02x,%02x,%d)", ireg->iis, ireg->cmsb,
126 ireg->clsb);
197 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
264 if ((ireg->iis != ISAR_IIS_DKEY) || ireg->cmsb || len) {
266 ireg->iis, ireg->cmsb, len);
314 if ((ireg->iis != ISAR_IIS_FIRM) || ireg->cmsb || len) {
316 ireg->iis, ireg->cmsb, len);
330 ireg->bstat = 0;
340 if ((ireg->iis != ISAR_IIS_STDSP) || ireg->cmsb || len) {
342 ireg->iis, ireg->cmsb, len);
351 while ((!ireg->bstat) && cnt) {
360 ireg->bstat);
367 ireg->iis = 0;
374 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
383 if ((ireg->cmsb == ISAR_CTRL_STST) && (ireg->clsb == 1)
384 && (ireg->par[0] == 0)) {
388 ireg->cmsb, ireg->clsb, ireg->par[0]);
392 ireg->iis = 0;
399 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
408 if ((ireg->cmsb == ISAR_CTRL_SWVER) && (ireg->clsb == 1))
410 ireg->par[0]);
413 ireg->cmsb, ireg->clsb, cnt);
493 struct isar_reg *ireg = bcs->hw.isar.reg;
495 if (!ireg->clsb) {
503 ireg->iis, ireg->cmsb, ireg->clsb);
505 ireg->iis, ireg->cmsb, ireg->clsb);
510 if ((skb = dev_alloc_skb(ireg->clsb))) {
511 rcv_mbox(cs, ireg, (u_char *)skb_put(skb, ireg->clsb));
520 if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
525 } else if (ireg->cmsb & HDLC_ERROR) {
528 ireg->cmsb, ireg->clsb);
530 if (ireg->cmsb & HDLC_ERR_RER)
532 if (ireg->cmsb & HDLC_ERR_CER)
538 if (ireg->cmsb & HDLC_FSD)
541 bcs->hw.isar.rcvidx += ireg->clsb;
542 rcv_mbox(cs, ireg, ptr);
543 if (ireg->cmsb & HDLC_FED) {
569 rcv_mbox(cs, ireg, bcs->hw.isar.rcvbuf);
570 bcs->hw.isar.rcvidx = ireg->clsb +
571 dle_count(bcs->hw.isar.rcvbuf, ireg->clsb);
574 ireg->clsb, bcs->hw.isar.rcvidx);
577 bcs->hw.isar.rcvbuf, ireg->clsb);
580 if (ireg->cmsb & SART_NMD) { /* ABORT */
605 if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
610 } else if (ireg->cmsb & HDLC_ERROR) {
613 ireg->cmsb, ireg->clsb);
617 if (ireg->cmsb & HDLC_FSD) {
621 bcs->hw.isar.rcvidx += ireg->clsb;
622 rcv_mbox(cs, ireg, ptr);
623 if (ireg->cmsb & HDLC_FED) {
647 if (ireg->cmsb & SART_NMD) { /* ABORT */
841 isar_pump_status_rsp(struct BCState *bcs, struct isar_reg *ireg) {
843 u_char ril = ireg->par[0];
853 switch(ireg->par[1]) {
1174 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
1177 get_irq_infos(cs, ireg);
1178 switch (ireg->iis & ISAR_IIS_MSCMSD) {
1180 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1184 ireg->iis, ireg->cmsb, ireg->clsb);
1190 ireg->bstat |= ireg->cmsb;
1191 check_send(cs, ireg->cmsb);
1195 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1196 if (ireg->cmsb == BSTEV_TBO)
1198 if (ireg->cmsb == BSTEV_RBO)
1204 ireg->iis>>6, ireg->cmsb);
1208 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1209 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1211 isar_pump_statev_modem(bcs, ireg->cmsb);
1213 isar_pump_statev_fax(bcs, ireg->cmsb);
1214 } else if (ireg->cmsb == PSEV_10MS_TIMER) {
1220 bcs->mode, ireg->cmsb);
1224 ireg->iis, ireg->cmsb, ireg->clsb);
1229 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1230 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1231 isar_pump_status_rsp(bcs, ireg);
1234 ireg->iis, ireg->cmsb, ireg->clsb);
1241 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1247 ireg->iis, ireg->cmsb);
1248 QuickHex(tp, (u_char *)ireg->par, ireg->clsb);
1253 rcv_mbox(cs, ireg, debbuf);
1256 ireg->cmsb);
1259 rcv_mbox(cs, ireg, debbuf);
1262 ireg->iis, ireg->cmsb, ireg->clsb);