Lines Matching refs:cs
31 ISACVersion(struct IsdnCardState *cs, char *s)
35 val = cs->readisac(cs, ISAC_RBCH);
40 ph_command(struct IsdnCardState *cs, unsigned int command)
42 if (cs->debug & L1_DEB_ISAC)
43 debugl1(cs, "ph_command %x", command);
44 cs->writeisac(cs, ISAC_CIX0, (command << 2) | 3);
49 isac_new_ph(struct IsdnCardState *cs)
51 switch (cs->dc.isac.ph_state) {
54 ph_command(cs, ISAC_CMD_DUI);
55 l1_msg(cs, HW_RESET | INDICATION, NULL);
58 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
61 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
64 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
67 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
70 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
73 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
76 l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL);
86 struct IsdnCardState *cs =
90 if (!cs)
92 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
93 if (cs->debug)
94 debugl1(cs, "D-Channel Busy cleared");
95 stptr = cs->stlist;
101 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
102 isac_new_ph(cs);
103 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
104 DChannel_proc_rcv(cs);
105 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
106 DChannel_proc_xmt(cs);
108 if (!test_bit(HW_ARCOFI, &cs->HW_Flags))
110 if (test_and_clear_bit(D_RX_MON1, &cs->event))
111 arcofi_fsm(cs, ARCOFI_RX_END, NULL);
112 if (test_and_clear_bit(D_TX_MON1, &cs->event))
113 arcofi_fsm(cs, ARCOFI_TX_END, NULL);
118 isac_empty_fifo(struct IsdnCardState *cs, int count)
122 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
123 debugl1(cs, "isac_empty_fifo");
125 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
126 if (cs->debug & L1_DEB_WARN)
127 debugl1(cs, "isac_empty_fifo overrun %d",
128 cs->rcvidx + count);
129 cs->writeisac(cs, ISAC_CMDR, 0x80);
130 cs->rcvidx = 0;
133 ptr = cs->rcvbuf + cs->rcvidx;
134 cs->rcvidx += count;
135 cs->readisacfifo(cs, ptr, count);
136 cs->writeisac(cs, ISAC_CMDR, 0x80);
137 if (cs->debug & L1_DEB_ISAC_FIFO) {
138 char *t = cs->dlog;
142 debugl1(cs, cs->dlog);
147 isac_fill_fifo(struct IsdnCardState *cs)
152 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
153 debugl1(cs, "isac_fill_fifo");
155 if (!cs->tx_skb)
158 count = cs->tx_skb->len;
167 ptr = cs->tx_skb->data;
168 skb_pull(cs->tx_skb, count);
169 cs->tx_cnt += count;
170 cs->writeisacfifo(cs, ptr, count);
171 cs->writeisac(cs, ISAC_CMDR, more ? 0x8 : 0xa);
172 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
173 debugl1(cs, "isac_fill_fifo dbusytimer running");
174 del_timer(&cs->dbusytimer);
176 init_timer(&cs->dbusytimer);
177 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
178 add_timer(&cs->dbusytimer);
179 if (cs->debug & L1_DEB_ISAC_FIFO) {
180 char *t = cs->dlog;
184 debugl1(cs, cs->dlog);
189 isac_interrupt(struct IsdnCardState *cs, u_char val)
195 if (cs->debug & L1_DEB_ISAC)
196 debugl1(cs, "ISAC interrupt %x", val);
198 exval = cs->readisac(cs, ISAC_RSTA);
201 if (cs->debug & L1_DEB_WARN)
202 debugl1(cs, "ISAC RDO");
204 cs->err_rx++;
208 if (cs->debug & L1_DEB_WARN)
209 debugl1(cs, "ISAC CRC error");
211 cs->err_crc++;
214 cs->writeisac(cs, ISAC_CMDR, 0x80);
216 count = cs->readisac(cs, ISAC_RBCL) & 0x1f;
219 isac_empty_fifo(cs, count);
220 if ((count = cs->rcvidx) > 0) {
221 cs->rcvidx = 0;
225 memcpy(skb_put(skb, count), cs->rcvbuf, count);
226 skb_queue_tail(&cs->rq, skb);
230 cs->rcvidx = 0;
231 schedule_event(cs, D_RCVBUFREADY);
234 isac_empty_fifo(cs, 32);
238 if (cs->debug & L1_DEB_WARN)
239 debugl1(cs, "ISAC RSC interrupt");
242 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
243 del_timer(&cs->dbusytimer);
244 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
245 schedule_event(cs, D_CLEARBUSY);
246 if (cs->tx_skb) {
247 if (cs->tx_skb->len) {
248 isac_fill_fifo(cs);
251 dev_kfree_skb_irq(cs->tx_skb);
252 cs->tx_cnt = 0;
253 cs->tx_skb = NULL;
256 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
257 cs->tx_cnt = 0;
258 isac_fill_fifo(cs);
260 schedule_event(cs, D_XMTBUFREADY);
264 exval = cs->readisac(cs, ISAC_CIR0);
265 if (cs->debug & L1_DEB_ISAC)
266 debugl1(cs, "ISAC CIR0 %02X", exval );
268 cs->dc.isac.ph_state = (exval >> 2) & 0xf;
269 if (cs->debug & L1_DEB_ISAC)
270 debugl1(cs, "ph_state change %x", cs->dc.isac.ph_state);
271 schedule_event(cs, D_L1STATECHANGE);
274 exval = cs->readisac(cs, ISAC_CIR1);
275 if (cs->debug & L1_DEB_ISAC)
276 debugl1(cs, "ISAC CIR1 %02X", exval );
281 if (cs->debug & L1_DEB_WARN)
282 debugl1(cs, "ISAC SIN interrupt");
285 exval = cs->readisac(cs, ISAC_EXIR);
286 if (cs->debug & L1_DEB_WARN)
287 debugl1(cs, "ISAC EXIR %02x", exval);
289 debugl1(cs, "ISAC XMR");
293 debugl1(cs, "ISAC XDU");
296 cs->err_tx++;
298 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
299 del_timer(&cs->dbusytimer);
300 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
301 schedule_event(cs, D_CLEARBUSY);
302 if (cs->tx_skb) { /* Restart frame */
303 skb_push(cs->tx_skb, cs->tx_cnt);
304 cs->tx_cnt = 0;
305 isac_fill_fifo(cs);
308 debugl1(cs, "ISAC XDU no skb");
312 v1 = cs->readisac(cs, ISAC_MOSR);
313 if (cs->debug & L1_DEB_MONITOR)
314 debugl1(cs, "ISAC MOSR %02x", v1);
317 if (!cs->dc.isac.mon_rx) {
318 if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
319 if (cs->debug & L1_DEB_WARN)
320 debugl1(cs, "ISAC MON RX out of memory!");
321 cs->dc.isac.mocr &= 0xf0;
322 cs->dc.isac.mocr |= 0x0a;
323 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
326 cs->dc.isac.mon_rxp = 0;
328 if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) {
329 cs->dc.isac.mocr &= 0xf0;
330 cs->dc.isac.mocr |= 0x0a;
331 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
332 cs->dc.isac.mon_rxp = 0;
333 if (cs->debug & L1_DEB_WARN)
334 debugl1(cs, "ISAC MON RX overflow!");
337 cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR0);
338 if (cs->debug & L1_DEB_MONITOR)
339 debugl1(cs, "ISAC MOR0 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp -1]);
340 if (cs->dc.isac.mon_rxp == 1) {
341 cs->dc.isac.mocr |= 0x04;
342 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
347 if (!cs->dc.isac.mon_rx) {
348 if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
349 if (cs->debug & L1_DEB_WARN)
350 debugl1(cs, "ISAC MON RX out of memory!");
351 cs->dc.isac.mocr &= 0x0f;
352 cs->dc.isac.mocr |= 0xa0;
353 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
356 cs->dc.isac.mon_rxp = 0;
358 if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) {
359 cs->dc.isac.mocr &= 0x0f;
360 cs->dc.isac.mocr |= 0xa0;
361 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
362 cs->dc.isac.mon_rxp = 0;
363 if (cs->debug & L1_DEB_WARN)
364 debugl1(cs, "ISAC MON RX overflow!");
367 cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR1);
368 if (cs->debug & L1_DEB_MONITOR)
369 debugl1(cs, "ISAC MOR1 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp -1]);
370 cs->dc.isac.mocr |= 0x40;
371 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
375 cs->dc.isac.mocr &= 0xf0;
376 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
377 cs->dc.isac.mocr |= 0x0a;
378 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
379 schedule_event(cs, D_RX_MON0);
382 cs->dc.isac.mocr &= 0x0f;
383 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
384 cs->dc.isac.mocr |= 0xa0;
385 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
386 schedule_event(cs, D_RX_MON1);
389 if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc &&
390 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
392 cs->dc.isac.mocr &= 0xf0;
393 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
394 cs->dc.isac.mocr |= 0x0a;
395 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
396 if (cs->dc.isac.mon_txc &&
397 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
398 schedule_event(cs, D_TX_MON0);
401 if (cs->dc.isac.mon_txc && (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) {
402 schedule_event(cs, D_TX_MON0);
405 cs->writeisac(cs, ISAC_MOX0,
406 cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
407 if (cs->debug & L1_DEB_MONITOR)
408 debugl1(cs, "ISAC %02x -> MOX0", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp -1]);
412 if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc &&
413 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
415 cs->dc.isac.mocr &= 0x0f;
416 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
417 cs->dc.isac.mocr |= 0xa0;
418 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
419 if (cs->dc.isac.mon_txc &&
420 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
421 schedule_event(cs, D_TX_MON1);
424 if (cs->dc.isac.mon_txc && (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) {
425 schedule_event(cs, D_TX_MON1);
428 cs->writeisac(cs, ISAC_MOX1,
429 cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
430 if (cs->debug & L1_DEB_MONITOR)
431 debugl1(cs, "ISAC %02x -> MOX1", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp -1]);
442 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
449 if (cs->debug & DEB_DLOG_HEX)
450 LogFrame(cs, skb->data, skb->len);
451 if (cs->debug & DEB_DLOG_VERBOSE)
452 dlogframe(cs, skb, 0);
453 spin_lock_irqsave(&cs->lock, flags);
454 if (cs->tx_skb) {
455 skb_queue_tail(&cs->sq, skb);
457 if (cs->debug & L1_DEB_LAPD)
458 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
461 cs->tx_skb = skb;
462 cs->tx_cnt = 0;
464 if (cs->debug & L1_DEB_LAPD)
465 Logl2Frame(cs, skb, "PH_DATA", 0);
467 isac_fill_fifo(cs);
469 spin_unlock_irqrestore(&cs->lock, flags);
472 spin_lock_irqsave(&cs->lock, flags);
473 if (cs->tx_skb) {
474 if (cs->debug & L1_DEB_WARN)
475 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
476 skb_queue_tail(&cs->sq, skb);
478 if (cs->debug & DEB_DLOG_HEX)
479 LogFrame(cs, skb->data, skb->len);
480 if (cs->debug & DEB_DLOG_VERBOSE)
481 dlogframe(cs, skb, 0);
482 cs->tx_skb = skb;
483 cs->tx_cnt = 0;
485 if (cs->debug & L1_DEB_LAPD)
486 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
488 isac_fill_fifo(cs);
490 spin_unlock_irqrestore(&cs->lock, flags);
494 if (cs->debug & L1_DEB_LAPD)
495 debugl1(cs, "-> PH_REQUEST_PULL");
497 if (!cs->tx_skb) {
504 spin_lock_irqsave(&cs->lock, flags);
505 if ((cs->dc.isac.ph_state == ISAC_IND_EI) ||
506 (cs->dc.isac.ph_state == ISAC_IND_DR) ||
507 (cs->dc.isac.ph_state == ISAC_IND_RS))
508 ph_command(cs, ISAC_CMD_TIM);
510 ph_command(cs, ISAC_CMD_RS);
511 spin_unlock_irqrestore(&cs->lock, flags);
514 spin_lock_irqsave(&cs->lock, flags);
515 ph_command(cs, ISAC_CMD_TIM);
516 spin_unlock_irqrestore(&cs->lock, flags);
519 spin_lock_irqsave(&cs->lock, flags);
520 ph_command(cs, ISAC_CMD_AR8);
521 spin_unlock_irqrestore(&cs->lock, flags);
524 spin_lock_irqsave(&cs->lock, flags);
530 if (test_bit(HW_IOM1, &cs->HW_Flags)) {
533 cs->writeisac(cs, ISAC_SPCR, 0xa);
534 cs->writeisac(cs, ISAC_ADF1, 0x2);
536 cs->writeisac(cs, ISAC_SPCR, val);
537 cs->writeisac(cs, ISAC_ADF1, 0xa);
541 cs->writeisac(cs, ISAC_SPCR, val);
543 cs->writeisac(cs, ISAC_ADF1, 0x8);
545 cs->writeisac(cs, ISAC_ADF1, 0x0);
547 spin_unlock_irqrestore(&cs->lock, flags);
550 skb_queue_purge(&cs->rq);
551 skb_queue_purge(&cs->sq);
552 if (cs->tx_skb) {
553 dev_kfree_skb_any(cs->tx_skb);
554 cs->tx_skb = NULL;
556 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
557 del_timer(&cs->dbusytimer);
558 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
559 schedule_event(cs, D_CLEARBUSY);
562 if (cs->debug & L1_DEB_WARN)
563 debugl1(cs, "isac_l1hw unknown %04x", pr);
569 setstack_isac(struct PStack *st, struct IsdnCardState *cs)
575 DC_Close_isac(struct IsdnCardState *cs)
577 kfree(cs->dc.isac.mon_rx);
578 cs->dc.isac.mon_rx = NULL;
579 kfree(cs->dc.isac.mon_tx);
580 cs->dc.isac.mon_tx = NULL;
584 dbusy_timer_handler(struct IsdnCardState *cs)
589 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
590 rbch = cs->readisac(cs, ISAC_RBCH);
591 star = cs->readisac(cs, ISAC_STAR);
592 if (cs->debug)
593 debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",
596 test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
597 stptr = cs->stlist;
604 test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
605 if (cs->tx_skb) {
606 dev_kfree_skb_any(cs->tx_skb);
607 cs->tx_cnt = 0;
608 cs->tx_skb = NULL;
611 debugl1(cs, "D-Channel Busy no skb");
613 cs->writeisac(cs, ISAC_CMDR, 0x01); /* Transmitter reset */
614 cs->irq_func(cs->irq, cs);
620 initisac(struct IsdnCardState *cs)
622 cs->setstack_d = setstack_isac;
623 cs->DC_Close = DC_Close_isac;
624 cs->dc.isac.mon_tx = NULL;
625 cs->dc.isac.mon_rx = NULL;
626 cs->writeisac(cs, ISAC_MASK, 0xff);
627 cs->dc.isac.mocr = 0xaa;
628 if (test_bit(HW_IOM1, &cs->HW_Flags)) {
630 cs->writeisac(cs, ISAC_ADF2, 0x0);
631 cs->writeisac(cs, ISAC_SPCR, 0xa);
632 cs->writeisac(cs, ISAC_ADF1, 0x2);
633 cs->writeisac(cs, ISAC_STCR, 0x70);
634 cs->writeisac(cs, ISAC_MODE, 0xc9);
637 if (!cs->dc.isac.adf2)
638 cs->dc.isac.adf2 = 0x80;
639 cs->writeisac(cs, ISAC_ADF2, cs->dc.isac.adf2);
640 cs->writeisac(cs, ISAC_SQXR, 0x2f);
641 cs->writeisac(cs, ISAC_SPCR, 0x00);
642 cs->writeisac(cs, ISAC_STCR, 0x70);
643 cs->writeisac(cs, ISAC_MODE, 0xc9);
644 cs->writeisac(cs, ISAC_TIMR, 0x00);
645 cs->writeisac(cs, ISAC_ADF1, 0x00);
647 ph_command(cs, ISAC_CMD_RS);
648 cs->writeisac(cs, ISAC_MASK, 0x0);
652 clear_pending_isac_ints(struct IsdnCardState *cs)
656 val = cs->readisac(cs, ISAC_STAR);
657 debugl1(cs, "ISAC STAR %x", val);
658 val = cs->readisac(cs, ISAC_MODE);
659 debugl1(cs, "ISAC MODE %x", val);
660 val = cs->readisac(cs, ISAC_ADF2);
661 debugl1(cs, "ISAC ADF2 %x", val);
662 val = cs->readisac(cs, ISAC_ISTA);
663 debugl1(cs, "ISAC ISTA %x", val);
665 eval = cs->readisac(cs, ISAC_EXIR);
666 debugl1(cs, "ISAC EXIR %x", eval);
668 val = cs->readisac(cs, ISAC_CIR0);
669 debugl1(cs, "ISAC CIR0 %x", val);
670 cs->dc.isac.ph_state = (val >> 2) & 0xf;
671 schedule_event(cs, D_L1STATECHANGE);
673 cs->writeisac(cs, ISAC_MASK, 0xFF);
677 setup_isac(struct IsdnCardState *cs)
679 INIT_WORK(&cs->tqueue, isac_bh);
680 cs->dbusytimer.function = (void *) dbusy_timer_handler;
681 cs->dbusytimer.data = (long) cs;
682 init_timer(&cs->dbusytimer);