Lines Matching refs:cs
34 static void ph_command(struct IsdnCardState *cs, unsigned int command);
35 static inline void cic_int(struct IsdnCardState *cs);
37 static void dbusy_timer_handler(struct IsdnCardState *cs);
38 static void dch_empty_fifo(struct IsdnCardState *cs, int count);
39 static void dch_fill_fifo(struct IsdnCardState *cs);
40 static inline void dch_int(struct IsdnCardState *cs);
41 static void dch_setstack(struct PStack *st, struct IsdnCardState *cs);
42 static void dch_init(struct IsdnCardState *cs);
46 static void bch_int(struct IsdnCardState *cs, u_char hscx);
49 static int bch_open_state(struct IsdnCardState *cs, struct BCState *bcs);
51 static void bch_init(struct IsdnCardState *cs, int hscx);
52 static void clear_pending_ints(struct IsdnCardState *cs);
58 ph_command(struct IsdnCardState *cs, unsigned int command)
60 if (cs->debug &L1_DEB_ISAC)
61 debugl1(cs, "ph_command (%#x) in (%#x)", command,
62 cs->dc.isac.ph_state);
66 cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E);
73 cic_int(struct IsdnCardState *cs)
77 event = cs->readisac(cs, IPACX_CIR0) >> 4;
78 if (cs->debug &L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event);
82 cs->dc.isac.ph_state = event;
83 schedule_event(cs, D_L1STATECHANGE);
96 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
102 if (cs->debug &DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
103 if (cs->debug &DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
104 if (cs->tx_skb) {
105 skb_queue_tail(&cs->sq, skb);
107 if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0);
110 cs->tx_skb = skb;
111 cs->tx_cnt = 0;
113 if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0);
115 dch_fill_fifo(cs);
120 if (cs->tx_skb) {
121 if (cs->debug & L1_DEB_WARN)
122 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
123 skb_queue_tail(&cs->sq, skb);
126 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
127 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
128 cs->tx_skb = skb;
129 cs->tx_cnt = 0;
131 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
133 dch_fill_fifo(cs);
138 if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL");
140 if (!cs->tx_skb) {
149 if ((cs->dc.isac.ph_state == IPACX_IND_RES) ||
150 (cs->dc.isac.ph_state == IPACX_IND_DR) ||
151 (cs->dc.isac.ph_state == IPACX_IND_DC))
152 ph_command(cs, IPACX_CMD_TIM);
154 ph_command(cs, IPACX_CMD_RES);
158 ph_command(cs, IPACX_CMD_AR8);
162 cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
163 cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
164 cda1_cr = cs->readisac(cs, IPACX_CDA1_CR);
165 cda2_cr = cs->readisac(cs, IPACX_CDA2_CR);
167 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x0a);
170 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x0a);
173 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x14);
176 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x14);
181 skb_queue_purge(&cs->rq);
182 skb_queue_purge(&cs->sq);
183 if (cs->tx_skb) {
184 dev_kfree_skb_any(cs->tx_skb);
185 cs->tx_skb = NULL;
187 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
188 del_timer(&cs->dbusytimer);
192 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr);
200 dbusy_timer_handler(struct IsdnCardState *cs)
205 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
206 rbchd = cs->readisac(cs, IPACX_RBCHD);
207 stard = cs->readisac(cs, IPACX_STARD);
208 if (cs->debug)
209 debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard);
211 set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
212 for (st = cs->stlist; st; st = st->next) {
217 clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
218 if (cs->tx_skb) {
219 dev_kfree_skb_any(cs->tx_skb);
220 cs->tx_cnt = 0;
221 cs->tx_skb = NULL;
224 debugl1(cs, "D-Channel Busy no skb");
226 cs->writeisac(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR
235 dch_empty_fifo(struct IsdnCardState *cs, int count)
239 if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO))
240 debugl1(cs, "dch_empty_fifo()");
243 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
244 if (cs->debug &L1_DEB_WARN)
245 debugl1(cs, "dch_empty_fifo() incoming message too large");
246 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
247 cs->rcvidx = 0;
251 ptr = cs->rcvbuf + cs->rcvidx;
252 cs->rcvidx += count;
254 cs->readisacfifo(cs, ptr, count);
255 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
257 if (cs->debug &L1_DEB_ISAC_FIFO) {
258 char *t = cs->dlog;
262 debugl1(cs, cs->dlog);
270 dch_fill_fifo(struct IsdnCardState *cs)
275 if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO))
276 debugl1(cs, "dch_fill_fifo()");
278 if (!cs->tx_skb) return;
279 count = cs->tx_skb->len;
289 ptr = cs->tx_skb->data;
290 skb_pull(cs->tx_skb, count);
291 cs->tx_cnt += count;
292 cs->writeisacfifo(cs, ptr, count);
293 cs->writeisac(cs, IPACX_CMDRD, cmd);
296 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
297 debugl1(cs, "dch_fill_fifo dbusytimer running");
298 del_timer(&cs->dbusytimer);
300 init_timer(&cs->dbusytimer);
301 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
302 add_timer(&cs->dbusytimer);
304 if (cs->debug &L1_DEB_ISAC_FIFO) {
305 char *t = cs->dlog;
309 debugl1(cs, cs->dlog);
317 dch_int(struct IsdnCardState *cs)
323 istad = cs->readisac(cs, IPACX_ISTAD);
329 rstad = cs->readisac(cs, IPACX_RSTAD);
332 if (cs->debug &L1_DEB_WARN)
333 debugl1(cs, "dch_int(): invalid frame");
335 if (cs->debug &L1_DEB_WARN)
336 debugl1(cs, "dch_int(): RDO");
338 if (cs->debug &L1_DEB_WARN)
339 debugl1(cs, "dch_int(): CRC error");
340 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
342 count = cs->readisac(cs, IPACX_RBCLD);
346 dch_empty_fifo(cs, count);
347 if ((count = cs->rcvidx) > 0) {
348 cs->rcvidx = 0;
352 memcpy(skb_put(skb, count), cs->rcvbuf, count);
353 skb_queue_tail(&cs->rq, skb);
357 cs->rcvidx = 0;
358 schedule_event(cs, D_RCVBUFREADY);
362 dch_empty_fifo(cs, D_FIFO_SIZE);
366 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): RFO");
367 cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES
371 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
372 del_timer(&cs->dbusytimer);
373 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
374 schedule_event(cs, D_CLEARBUSY);
375 if (cs->tx_skb) {
376 if (cs->tx_skb->len) {
377 dch_fill_fifo(cs);
381 dev_kfree_skb_irq(cs->tx_skb);
382 cs->tx_skb = NULL;
383 cs->tx_cnt = 0;
386 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
387 cs->tx_cnt = 0;
388 dch_fill_fifo(cs);
391 schedule_event(cs, D_XMTBUFREADY);
397 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): XDU");
398 if (cs->tx_skb) {
399 skb_push(cs->tx_skb, cs->tx_cnt); // retransmit
400 cs->tx_cnt = 0;
401 dch_fill_fifo(cs);
404 debugl1(cs, "ISAC XDU no skb");
412 dch_setstack(struct PStack *st, struct IsdnCardState *cs)
420 dch_init(struct IsdnCardState *cs)
424 cs->setstack_d = dch_setstack;
426 cs->dbusytimer.function = (void *) dbusy_timer_handler;
427 cs->dbusytimer.data = (long) cs;
428 init_timer(&cs->dbusytimer);
430 cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD
431 cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter
432 cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go
433 cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel
453 spin_lock_irqsave(&bcs->cs->lock, flags);
462 spin_unlock_irqrestore(&bcs->cs->lock, flags);
465 spin_lock_irqsave(&bcs->cs->lock, flags);
474 spin_unlock_irqrestore(&bcs->cs->lock, flags);
484 spin_lock_irqsave(&bcs->cs->lock, flags);
487 spin_unlock_irqrestore(&bcs->cs->lock, flags);
494 spin_lock_irqsave(&bcs->cs->lock, flags);
498 spin_unlock_irqrestore(&bcs->cs->lock, flags);
511 struct IsdnCardState *cs;
514 cs = bcs->cs;
516 if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO))
517 debugl1(cs, "bch_empty_fifo()");
521 if (cs->debug &L1_DEB_WARN)
522 debugl1(cs, "bch_empty_fifo() incoming packet too large");
523 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
530 while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB);
531 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
536 if (cs->debug &L1_DEB_HSCX_FIFO) {
541 debugl1(cs, bcs->blog);
551 struct IsdnCardState *cs;
555 cs = bcs->cs;
556 if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO))
557 debugl1(cs, "bch_fill_fifo()");
576 while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++);
577 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a));
579 if (cs->debug &L1_DEB_HSCX_FIFO) {
584 debugl1(cs, bcs->blog);
592 bch_int(struct IsdnCardState *cs, u_char hscx)
600 bcs = cs->bcs + hscx;
601 istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB);
608 rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB);
611 if (cs->debug &L1_DEB_WARN)
612 debugl1(cs, "bch_int() B-%d: invalid frame", hscx);
614 if (cs->debug &L1_DEB_WARN)
615 debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode);
617 if (cs->debug &L1_DEB_WARN)
618 debugl1(cs, "bch_int() B-%d: CRC error", hscx);
619 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
622 count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) &(B_FIFO_SIZE-1);
626 if (cs->debug &L1_DEB_HSCX_FIFO)
627 debugl1(cs, "bch_int Frame %d", count);
657 if (cs->debug &L1_DEB_WARN)
658 debugl1(cs, "bch_int() B-%d: RFO error", hscx);
659 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES
702 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES
703 if (cs->debug &L1_DEB_WARN)
704 debugl1(cs, "bch_int() B-%d XDU error", hscx);
714 struct IsdnCardState *cs = bcs->cs;
718 if (cs->debug & L1_DEB_HSCX)
719 debugl1(cs, "mode_bch() switch B-% mode %d chan %d", hscx, mode, bc);
726 cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);
727 cs->writeisac(cs, IPACX_BCHA_CR, 0x88);
731 cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);
732 cs->writeisac(cs, IPACX_BCHB_CR, 0x88);
737 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off
738 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj.
739 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off
740 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
743 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode
744 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000
745 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
746 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
749 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0
750 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled
751 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
752 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
781 bch_open_state(struct IsdnCardState *cs, struct BCState *bcs)
827 bch_init(struct IsdnCardState *cs, int hscx)
829 cs->bcs[hscx].BC_SetStack = bch_setstack;
830 cs->bcs[hscx].BC_Close = bch_close_state;
831 cs->bcs[hscx].hw.hscx.hscx = hscx;
832 cs->bcs[hscx].cs = cs;
833 bch_mode(cs->bcs + hscx, 0, hscx);
845 interrupt_ipacx(struct IsdnCardState *cs)
849 while ((ista = cs->readisac(cs, IPACX_ISTA))) {
853 if (ista &0x80) bch_int(cs, 0); // B channel interrupts
854 if (ista &0x40) bch_int(cs, 1);
856 if (ista &0x01) dch_int(cs); // D channel
857 if (ista &0x10) cic_int(cs); // Layer 1 state
865 clear_pending_ints(struct IsdnCardState *cs)
870 cs->writeisac(cs, IPACX_MASK, 0xff);
871 cs->writeisac(cs, IPACX_MASKD, 0xff);
872 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff);
873 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff);
875 ista = cs->readisac(cs, IPACX_ISTA);
876 if (ista &0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB);
877 if (ista &0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB);
878 if (ista &0x10) cs->readisac(cs, IPACX_CIR0);
879 if (ista &0x01) cs->readisac(cs, IPACX_ISTAD);
887 init_ipacx(struct IsdnCardState *cs, int part)
893 clear_pending_ints(cs);
894 bch_init(cs, 0);
895 bch_init(cs, 1);
896 dch_init(cs);
899 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK);
900 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK);
901 cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK);
902 cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register
905 cs->writeisac(cs, IPACX_CMDRD, 0x41);
906 cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41);
907 cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41);
908 ph_command(cs, IPACX_CMD_RES);