Lines Matching refs:cs
27 dummyf(struct IsdnCardState *cs, u_char * data, int size)
33 ReadReg(struct IsdnCardState *cs, int data, u_char reg)
38 if (cs->hw.hfcD.cip != reg) {
39 cs->hw.hfcD.cip = reg;
40 byteout(cs->hw.hfcD.addr | 1, reg);
42 ret = bytein(cs->hw.hfcD.addr);
44 if (cs->debug & L1_DEB_HSCX_FIFO && (data != 2))
45 debugl1(cs, "t3c RD %02x %02x", reg, ret);
48 ret = bytein(cs->hw.hfcD.addr | 1);
53 WriteReg(struct IsdnCardState *cs, int data, u_char reg, u_char value)
55 if (cs->hw.hfcD.cip != reg) {
56 cs->hw.hfcD.cip = reg;
57 byteout(cs->hw.hfcD.addr | 1, reg);
60 byteout(cs->hw.hfcD.addr, value);
62 if (cs->debug & L1_DEB_HSCX_FIFO && (data != HFCD_DATA_NODEB))
63 debugl1(cs, "t3c W%c %02x %02x", data ? 'D' : 'C', reg, value);
70 readreghfcd(struct IsdnCardState *cs, u_char offset)
72 return(ReadReg(cs, HFCD_DATA, offset));
76 writereghfcd(struct IsdnCardState *cs, u_char offset, u_char value)
78 WriteReg(cs, HFCD_DATA, offset, value);
82 WaitForBusy(struct IsdnCardState *cs)
86 while (!(ReadReg(cs, HFCD_DATA, HFCD_STAT) & HFCD_BUSY) && to) {
96 WaitNoBusy(struct IsdnCardState *cs)
100 while ((ReadReg(cs, HFCD_STATUS, HFCD_STATUS) & HFCD_BUSY) && to) {
110 SelFiFo(struct IsdnCardState *cs, u_char FiFo)
114 if (cs->hw.hfcD.fifo == FiFo)
130 debugl1(cs, "SelFiFo Error");
133 cs->hw.hfcD.fifo = FiFo;
134 WaitNoBusy(cs);
135 cs->BC_Write_Reg(cs, HFCD_DATA, cip, 0);
136 WaitForBusy(cs);
146 return (bcs->cs->hw.hfcD.bfifosize);
149 s += bcs->cs->hw.hfcD.bfifosize;
150 s = bcs->cs->hw.hfcD.bfifosize - s;
155 GetFreeFifoBytes_D(struct IsdnCardState *cs)
159 if (cs->hw.hfcD.f1 == cs->hw.hfcD.f2)
160 return (cs->hw.hfcD.dfifosize);
161 s = cs->hw.hfcD.send[cs->hw.hfcD.f1] - cs->hw.hfcD.send[cs->hw.hfcD.f2];
163 s += cs->hw.hfcD.dfifosize;
164 s = cs->hw.hfcD.dfifosize - s;
169 ReadZReg(struct IsdnCardState *cs, u_char reg)
173 WaitNoBusy(cs);
174 val = 256 * ReadReg(cs, HFCD_DATA, reg | HFCB_Z_HIGH);
175 WaitNoBusy(cs);
176 val += ReadReg(cs, HFCD_DATA, reg | HFCB_Z_LOW);
185 struct IsdnCardState *cs = bcs->cs;
190 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
191 debugl1(cs, "hfc_empty_fifo");
194 if (cs->debug & L1_DEB_WARN)
195 debugl1(cs, "hfc_empty_fifo: incoming packet too large");
198 WaitNoBusy(cs);
199 ReadReg(cs, HFCD_DATA_NODEB, cip);
203 if (cs->debug & L1_DEB_WARN)
204 debugl1(cs, "hfc_empty_fifo: incoming packet too small");
209 while ((idx++ < count) && WaitNoBusy(cs))
210 ReadReg(cs, HFCD_DATA_NODEB, cip);
219 if (!WaitNoBusy(cs))
221 *ptr = ReadReg(cs, HFCD_DATA_NODEB, cip);
226 debugl1(cs, "RFIFO BUSY error");
231 WaitNoBusy(cs);
232 chksum = (ReadReg(cs, HFCD_DATA, cip) << 8);
233 WaitNoBusy(cs);
234 chksum += ReadReg(cs, HFCD_DATA, cip);
235 WaitNoBusy(cs);
236 stat = ReadReg(cs, HFCD_DATA, cip);
237 if (cs->debug & L1_DEB_HSCX)
238 debugl1(cs, "hfc_empty_fifo %d chksum %x stat %x",
241 debugl1(cs, "FIFO CRC error");
250 WaitForBusy(cs);
251 WaitNoBusy(cs);
252 stat = ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F2_INC |
254 WaitForBusy(cs);
261 struct IsdnCardState *cs = bcs->cs;
270 SelFiFo(cs, HFCB_SEND | HFCB_CHANNEL(bcs->channel));
272 WaitNoBusy(cs);
273 bcs->hw.hfc.f1 = ReadReg(cs, HFCD_DATA, cip);
274 WaitNoBusy(cs);
276 WaitNoBusy(cs);
277 bcs->hw.hfc.f2 = ReadReg(cs, HFCD_DATA, cip);
278 bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_CHANNEL(bcs->channel));
279 if (cs->debug & L1_DEB_HSCX)
280 debugl1(cs, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
287 if (cs->debug & L1_DEB_HSCX)
288 debugl1(cs, "hfc_fill_fifo more as 30 frames");
292 if (cs->debug & L1_DEB_HSCX)
293 debugl1(cs, "hfc_fill_fifo %d count(%ld/%d),%lx",
297 if (cs->debug & L1_DEB_HSCX)
298 debugl1(cs, "hfc_fill_fifo no fifo mem");
303 WaitForBusy(cs);
304 WaitNoBusy(cs);
305 WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
307 if (!WaitNoBusy(cs))
309 WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx]);
313 debugl1(cs, "FIFO Send BUSY error");
328 WaitForBusy(cs);
329 WaitNoBusy(cs);
330 ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F1_INC | HFCB_SEND | HFCB_CHANNEL(bcs->channel));
331 WaitForBusy(cs);
339 struct IsdnCardState *cs = bcs->cs;
341 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
343 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
345 debugl1(cs,"send_data %d blocked", bcs->channel);
351 struct IsdnCardState *cs = bcs->cs;
359 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
360 debugl1(cs,"rec_data %d blocked", bcs->channel);
363 SelFiFo(cs, HFCB_REC | HFCB_CHANNEL(bcs->channel));
365 WaitNoBusy(cs);
366 f1 = ReadReg(cs, HFCD_DATA, cip);
368 WaitNoBusy(cs);
369 f2 = ReadReg(cs, HFCD_DATA, cip);
371 if (cs->debug & L1_DEB_HSCX)
372 debugl1(cs, "hfc rec %d f1(%d) f2(%d)",
374 z1 = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_CHANNEL(bcs->channel));
375 z2 = ReadZReg(cs, HFCB_FIFO | HFCB_Z2 | HFCB_REC | HFCB_CHANNEL(bcs->channel));
378 rcnt += cs->hw.hfcD.bfifosize;
380 if (cs->debug & L1_DEB_HSCX)
381 debugl1(cs, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
396 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
405 struct IsdnCardState *cs = bcs->cs;
407 if (cs->debug & L1_DEB_HSCX)
408 debugl1(cs, "HFCD bchannel mode %d bchan %d/%d",
415 cs->hw.hfcD.conn |= 0x18;
416 cs->hw.hfcD.sctrl &= ~SCTRL_B2_ENA;
418 cs->hw.hfcD.conn |= 0x3;
419 cs->hw.hfcD.sctrl &= ~SCTRL_B1_ENA;
424 cs->hw.hfcD.ctmt |= 2;
425 cs->hw.hfcD.conn &= ~0x18;
426 cs->hw.hfcD.sctrl |= SCTRL_B2_ENA;
428 cs->hw.hfcD.ctmt |= 1;
429 cs->hw.hfcD.conn &= ~0x3;
430 cs->hw.hfcD.sctrl |= SCTRL_B1_ENA;
435 cs->hw.hfcD.ctmt &= ~2;
436 cs->hw.hfcD.conn &= ~0x18;
437 cs->hw.hfcD.sctrl |= SCTRL_B2_ENA;
439 cs->hw.hfcD.ctmt &= ~1;
440 cs->hw.hfcD.conn &= ~0x3;
441 cs->hw.hfcD.sctrl |= SCTRL_B1_ENA;
445 WriteReg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl);
446 WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt);
447 WriteReg(cs, HFCD_DATA, HFCD_CONN, cs->hw.hfcD.conn);
459 spin_lock_irqsave(&bcs->cs->lock, flags);
465 bcs->cs->BC_Send_Data(bcs);
467 spin_unlock_irqrestore(&bcs->cs->lock, flags);
470 spin_lock_irqsave(&bcs->cs->lock, flags);
476 bcs->cs->BC_Send_Data(bcs);
478 spin_unlock_irqrestore(&bcs->cs->lock, flags);
488 spin_lock_irqsave(&bcs->cs->lock, flags);
491 spin_unlock_irqrestore(&bcs->cs->lock, flags);
498 spin_lock_irqsave(&bcs->cs->lock, flags);
502 spin_unlock_irqrestore(&bcs->cs->lock, flags);
524 open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs)
554 struct IsdnCardState *cs =
557 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
558 switch (cs->dc.hfcd.ph_state) {
560 l1_msg(cs, HW_RESET | INDICATION, NULL);
563 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
566 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
569 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
572 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
578 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
579 DChannel_proc_rcv(cs);
580 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
581 DChannel_proc_xmt(cs);
585 int receive_dmsg(struct IsdnCardState *cs)
595 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
596 debugl1(cs, "rec_dmsg blocked");
599 SelFiFo(cs, 4 | HFCD_REC);
601 WaitNoBusy(cs);
602 f1 = cs->readisac(cs, cip) & 0xf;
604 WaitNoBusy(cs);
605 f2 = cs->readisac(cs, cip) & 0xf;
607 z1 = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_REC);
608 z2 = ReadZReg(cs, HFCD_FIFO | HFCD_Z2 | HFCD_REC);
611 rcnt += cs->hw.hfcD.dfifosize;
613 if (cs->debug & L1_DEB_ISAC)
614 debugl1(cs, "hfcd recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
619 if (cs->debug & L1_DEB_WARN)
620 debugl1(cs, "empty_fifo d: incoming packet too large");
622 if (!(WaitNoBusy(cs)))
624 ReadReg(cs, HFCD_DATA_NODEB, cip);
628 if (cs->debug & L1_DEB_WARN)
629 debugl1(cs, "empty_fifo d: incoming packet too small");
630 while ((idx++ < rcnt) && WaitNoBusy(cs))
631 ReadReg(cs, HFCD_DATA_NODEB, cip);
635 if (!(WaitNoBusy(cs)))
637 *ptr = ReadReg(cs, HFCD_DATA_NODEB, cip);
642 debugl1(cs, "RFIFO D BUSY error");
647 cs->err_rx++;
650 WaitNoBusy(cs);
651 chksum = (ReadReg(cs, HFCD_DATA, cip) << 8);
652 WaitNoBusy(cs);
653 chksum += ReadReg(cs, HFCD_DATA, cip);
654 WaitNoBusy(cs);
655 stat = ReadReg(cs, HFCD_DATA, cip);
656 if (cs->debug & L1_DEB_ISAC)
657 debugl1(cs, "empty_dfifo chksum %x stat %x",
660 debugl1(cs, "FIFO CRC error");
664 cs->err_crc++;
667 skb_queue_tail(&cs->rq, skb);
668 schedule_event(cs, D_RCVBUFREADY);
673 WaitForBusy(cs);
675 WaitNoBusy(cs);
676 stat = ReadReg(cs, HFCD_DATA, cip);
677 WaitForBusy(cs);
679 WaitNoBusy(cs);
680 f2 = cs->readisac(cs, cip) & 0xf;
682 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
687 hfc_fill_dfifo(struct IsdnCardState *cs)
693 if (!cs->tx_skb)
695 if (cs->tx_skb->len <= 0)
698 SelFiFo(cs, 4 | HFCD_SEND);
700 WaitNoBusy(cs);
701 cs->hw.hfcD.f1 = ReadReg(cs, HFCD_DATA, cip) & 0xf;
702 WaitNoBusy(cs);
704 cs->hw.hfcD.f2 = ReadReg(cs, HFCD_DATA, cip) & 0xf;
705 cs->hw.hfcD.send[cs->hw.hfcD.f1] = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_SEND);
706 if (cs->debug & L1_DEB_ISAC)
707 debugl1(cs, "hfc_fill_Dfifo f1(%d) f2(%d) z1(%x)",
708 cs->hw.hfcD.f1, cs->hw.hfcD.f2,
709 cs->hw.hfcD.send[cs->hw.hfcD.f1]);
710 fcnt = cs->hw.hfcD.f1 - cs->hw.hfcD.f2;
714 if (cs->debug & L1_DEB_HSCX)
715 debugl1(cs, "hfc_fill_Dfifo more as 14 frames");
718 count = GetFreeFifoBytes_D(cs);
719 if (cs->debug & L1_DEB_ISAC)
720 debugl1(cs, "hfc_fill_Dfifo count(%ld/%d)",
721 cs->tx_skb->len, count);
722 if (count < cs->tx_skb->len) {
723 if (cs->debug & L1_DEB_ISAC)
724 debugl1(cs, "hfc_fill_Dfifo no fifo mem");
729 WaitForBusy(cs);
730 WaitNoBusy(cs);
731 WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx++]);
732 while (idx < cs->tx_skb->len) {
733 if (!(WaitNoBusy(cs)))
735 WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx]);
738 if (idx != cs->tx_skb->len) {
739 debugl1(cs, "DFIFO Send BUSY error");
742 WaitForBusy(cs);
743 WaitNoBusy(cs);
744 ReadReg(cs, HFCD_DATA, HFCD_FIFO | HFCD_F1_INC | HFCD_SEND);
745 dev_kfree_skb_any(cs->tx_skb);
746 cs->tx_skb = NULL;
747 WaitForBusy(cs);
752 struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel)
754 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
755 return(&cs->bcs[0]);
756 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
757 return(&cs->bcs[1]);
763 hfc2bds0_interrupt(struct IsdnCardState *cs, u_char val)
769 if (cs->debug & L1_DEB_ISAC)
770 debugl1(cs, "HFCD irq %x %s", val,
771 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
773 val &= cs->hw.hfcD.int_m1;
775 exval = cs->readisac(cs, HFCD_STATES) & 0xf;
776 if (cs->debug & L1_DEB_ISAC)
777 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcd.ph_state,
779 cs->dc.hfcd.ph_state = exval;
780 schedule_event(cs, D_L1STATECHANGE);
784 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
785 cs->hw.hfcD.int_s1 |= val;
788 if (cs->hw.hfcD.int_s1 & 0x18) {
790 val = cs->hw.hfcD.int_s1;
791 cs->hw.hfcD.int_s1 = exval;
794 if (!(bcs=Sel_BCS(cs, 0))) {
795 if (cs->debug)
796 debugl1(cs, "hfcd spurious 0x08 IRQ");
801 if (!(bcs=Sel_BCS(cs, 1))) {
802 if (cs->debug)
803 debugl1(cs, "hfcd spurious 0x10 IRQ");
808 if (!(bcs=Sel_BCS(cs, 0))) {
809 if (cs->debug)
810 debugl1(cs, "hfcd spurious 0x01 IRQ");
813 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
815 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
817 debugl1(cs,"fill_data %d blocked", bcs->channel);
820 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
822 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
824 debugl1(cs,"fill_data %d blocked", bcs->channel);
832 if (!(bcs=Sel_BCS(cs, 1))) {
833 if (cs->debug)
834 debugl1(cs, "hfcd spurious 0x02 IRQ");
837 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
839 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
841 debugl1(cs,"fill_data %d blocked", bcs->channel);
844 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
846 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
848 debugl1(cs,"fill_data %d blocked", bcs->channel);
856 receive_dmsg(cs);
859 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
860 del_timer(&cs->dbusytimer);
861 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
862 schedule_event(cs, D_CLEARBUSY);
863 if (cs->tx_skb) {
864 if (cs->tx_skb->len) {
865 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
866 hfc_fill_dfifo(cs);
867 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
869 debugl1(cs, "hfc_fill_dfifo irq blocked");
873 dev_kfree_skb_irq(cs->tx_skb);
874 cs->tx_cnt = 0;
875 cs->tx_skb = NULL;
878 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
879 cs->tx_cnt = 0;
880 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
881 hfc_fill_dfifo(cs);
882 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
884 debugl1(cs, "hfc_fill_dfifo irq blocked");
887 schedule_event(cs, D_XMTBUFREADY);
890 if (cs->hw.hfcD.int_s1 && count--) {
891 val = cs->hw.hfcD.int_s1;
892 cs->hw.hfcD.int_s1 = 0;
893 if (cs->debug & L1_DEB_ISAC)
894 debugl1(cs, "HFCD irq %x loop %d", val, 15-count);
903 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
909 if (cs->debug & DEB_DLOG_HEX)
910 LogFrame(cs, skb->data, skb->len);
911 if (cs->debug & DEB_DLOG_VERBOSE)
912 dlogframe(cs, skb, 0);
913 spin_lock_irqsave(&cs->lock, flags);
914 if (cs->tx_skb) {
915 skb_queue_tail(&cs->sq, skb);
917 if (cs->debug & L1_DEB_LAPD)
918 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
921 cs->tx_skb = skb;
922 cs->tx_cnt = 0;
924 if (cs->debug & L1_DEB_LAPD)
925 Logl2Frame(cs, skb, "PH_DATA", 0);
927 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
928 hfc_fill_dfifo(cs);
929 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
931 debugl1(cs, "hfc_fill_dfifo blocked");
934 spin_unlock_irqrestore(&cs->lock, flags);
937 spin_lock_irqsave(&cs->lock, flags);
938 if (cs->tx_skb) {
939 if (cs->debug & L1_DEB_WARN)
940 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
941 skb_queue_tail(&cs->sq, skb);
942 spin_unlock_irqrestore(&cs->lock, flags);
945 if (cs->debug & DEB_DLOG_HEX)
946 LogFrame(cs, skb->data, skb->len);
947 if (cs->debug & DEB_DLOG_VERBOSE)
948 dlogframe(cs, skb, 0);
949 cs->tx_skb = skb;
950 cs->tx_cnt = 0;
952 if (cs->debug & L1_DEB_LAPD)
953 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
955 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
956 hfc_fill_dfifo(cs);
957 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
959 debugl1(cs, "hfc_fill_dfifo blocked");
960 spin_unlock_irqrestore(&cs->lock, flags);
964 if (cs->debug & L1_DEB_LAPD)
965 debugl1(cs, "-> PH_REQUEST_PULL");
967 if (!cs->tx_skb) {
974 spin_lock_irqsave(&cs->lock, flags);
975 cs->writeisac(cs, HFCD_STATES, HFCD_LOAD_STATE | 3); /* HFC ST 3 */
977 cs->writeisac(cs, HFCD_STATES, 3); /* HFC ST 2 */
978 cs->hw.hfcD.mst_m |= HFCD_MASTER;
979 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
980 cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION);
981 spin_unlock_irqrestore(&cs->lock, flags);
982 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
985 spin_lock_irqsave(&cs->lock, flags);
986 cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION);
987 spin_unlock_irqrestore(&cs->lock, flags);
990 spin_lock_irqsave(&cs->lock, flags);
991 cs->hw.hfcD.mst_m &= ~HFCD_MASTER;
992 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
993 spin_unlock_irqrestore(&cs->lock, flags);
996 spin_lock_irqsave(&cs->lock, flags);
997 cs->hw.hfcD.mst_m |= HFCD_MASTER;
998 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
999 spin_unlock_irqrestore(&cs->lock, flags);
1002 if (cs->debug & L1_DEB_WARN)
1003 debugl1(cs, "hfcd_l1hw unknown pr %4x", pr);
1009 setstack_hfcd(struct PStack *st, struct IsdnCardState *cs)
1015 hfc_dbusy_timer(struct IsdnCardState *cs)
1035 init2bds0(struct IsdnCardState *cs)
1037 cs->setstack_d = setstack_hfcd;
1038 if (!cs->hw.hfcD.send)
1039 cs->hw.hfcD.send = init_send_hfcd(16);
1040 if (!cs->bcs[0].hw.hfc.send)
1041 cs->bcs[0].hw.hfc.send = init_send_hfcd(32);
1042 if (!cs->bcs[1].hw.hfc.send)
1043 cs->bcs[1].hw.hfc.send = init_send_hfcd(32);
1044 cs->BC_Send_Data = &hfc_send_data;
1045 cs->bcs[0].BC_SetStack = setstack_2b;
1046 cs->bcs[1].BC_SetStack = setstack_2b;
1047 cs->bcs[0].BC_Close = close_2bs0;
1048 cs->bcs[1].BC_Close = close_2bs0;
1049 mode_2bs0(cs->bcs, 0, 0);
1050 mode_2bs0(cs->bcs + 1, 0, 1);
1054 release2bds0(struct IsdnCardState *cs)
1056 kfree(cs->bcs[0].hw.hfc.send);
1057 cs->bcs[0].hw.hfc.send = NULL;
1058 kfree(cs->bcs[1].hw.hfc.send);
1059 cs->bcs[1].hw.hfc.send = NULL;
1060 kfree(cs->hw.hfcD.send);
1061 cs->hw.hfcD.send = NULL;
1065 set_cs_func(struct IsdnCardState *cs)
1067 cs->readisac = &readreghfcd;
1068 cs->writeisac = &writereghfcd;
1069 cs->readisacfifo = &dummyf;
1070 cs->writeisacfifo = &dummyf;
1071 cs->BC_Read_Reg = &ReadReg;
1072 cs->BC_Write_Reg = &WriteReg;
1073 cs->dbusytimer.function = (void *) hfc_dbusy_timer;
1074 cs->dbusytimer.data = (long) cs;
1075 init_timer(&cs->dbusytimer);
1076 INIT_WORK(&cs->tqueue, hfcd_bh);