Lines Matching refs:base
84 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80));
90 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);
96 readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
102 writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
109 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0)));
115 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);
123 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,
131 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \
133 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
135 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \
137 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base, \
150 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
159 val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40);
171 val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80);
180 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
189 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);
190 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);
198 release_region(cs->hw.ax.base & 0xffffffc0, 128);
365 printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
387 cs->hw.ax.base = pci_ioaddr5 + 0x00;
403 cs->hw.ax.base = pci_ioaddr4 + 0x08;
408 cs->hw.ax.base = pci_ioaddr3 + 0x10;
413 cs->hw.ax.base = pci_ioaddr2 + 0x20;
419 cs->hw.ax.data_adr = cs->hw.ax.base + 4;
425 cs->hw.ax.base,
445 readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));