Lines Matching refs:base
80 * siimage_selreg - return register base
92 unsigned long base = (unsigned long)hwif->hwif_data;
93 base += 0xA0 + r;
95 base += (hwif->channel << 6);
97 base += (hwif->channel << 4);
98 return base;
102 * siimage_seldev - return register base
114 unsigned long base = (unsigned long)hwif->hwif_data;
115 base += 0xA0 + r;
117 base += (hwif->channel << 6);
119 base += (hwif->channel << 4);
120 base |= drive->select.b.unit << drive->select.b.unit;
121 return base;
137 unsigned long base = (unsigned long) hwif->hwif_data;
141 scsc = hwif->INB(base + 0x4A);
290 unsigned long base = (unsigned long)hwif->hwif_data;
299 scsc = hwif->INB(base + 0x4A);
300 mode = hwif->INB(base + addr_mask);
350 hwif->OUTB(mode, base + addr_mask);
411 unsigned long base = (unsigned long)hwif->hwif_data;
415 u32 ext_stat = readl((void __iomem *)(base + 0x10));
780 unsigned long base;
797 base = (unsigned long)addr;
799 base += 0xC0;
801 base += 0x80;
808 hw.io_ports[IDE_DATA_OFFSET] = base;
809 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
810 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
811 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
812 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
813 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
814 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
815 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
816 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
821 base = (unsigned long)addr;
823 base += 0x80;
824 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
825 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
826 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
827 hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140;
828 hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144;
829 hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148;
839 base = (unsigned long) addr;
841 hwif->dma_base = base + (ch ? 0x08 : 0x00);