Lines Matching refs:BIT2
514 #define TRANSMIT_DATA BIT2
532 #define RXSTATUS_ABORT BIT2
533 #define RXSTATUS_PARITY_ERROR BIT2
571 #define TXSTATUS_ALL_SENT BIT2
591 #define MISCSTATUS_DPLL_NO_SYNC BIT2
617 #define SICR_DPLL_NO_SYNC BIT2
643 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
651 #define TXSTATUS_ALL_SENT BIT2
672 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
1610 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1650 * BIT2 EOB End of Buffer. This interrupt occurs when a
1679 if ( status & BIT2 ) {
5486 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5489 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5575 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5578 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5681 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5684 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5961 RegValue |= BIT4+BIT3+BIT2;
6018 RegValue |= BIT4+BIT3+BIT2;
7332 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {