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  • only in /netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/char/

Lines Matching refs:Byte_t

162 static Byte_t RData[RDATASIZE] = {
183 static Byte_t RRegData[RREGDATASIZE] = {
210 static Byte_t sBitMapClrTbl[8] = {
214 static Byte_t sBitMapSetTbl[8] = {
238 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
245 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
248 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
253 int IRQNum, Byte_t Frequency, int PeriodicOnly);
2533 Byte_t Frequency: A flag identifying the frequency
2581 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2608 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2653 Byte_t Frequency: A flag identifying the frequency
2701 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2763 Byte_t AiopID; /* ID byte from AIOP */
2790 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2824 Byte_t *ChR;
2826 static Byte_t R[4];
2878 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2879 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2880 ChP->BaudDiv[2] = (Byte_t) brd9600;
2881 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2884 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2885 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2890 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2891 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2896 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2897 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2902 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2903 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2908 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2909 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2914 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2915 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2923 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2924 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2930 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2931 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2968 Byte_t R[4];
2994 Byte_t Ch; /* channel number within AIOP */
3008 Ch = (Byte_t) sGetChanNum(ChP);
3036 Byte_t Ch; /* channel number within AIOP */
3050 Ch = (Byte_t) sGetChanNum(ChP);
3065 Byte_t Data; The transmit data byte
3073 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3075 Byte_t DWBuf[4]; /* buffer for double word writes */
3137 Byte_t Mask; /* Interrupt Mask Register */
3140 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3144 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3181 Byte_t Mask; /* Interrupt Mask Register */
3184 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3186 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3195 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3207 Byte_t val;